Balanced prefetching aggressiveness controller for NoC-based multiprocessor

The performance gap between memory hierarchy and processor is a well-known issue and the prefetching approach is often used to minimize this problem. This technique performs a data prefetch in memory and makes it available in the private cache before its request. Thus, as more prefetching transactions are performed (very aggressive prefetching aggressiveness), the miss rate in the first levels of cache tends to be lower. However, a very aggressive prefetching can cause cache pollution, increase network traffic, and thereby degrade the system performance. In a multiprocessors platform, the prefetching of a core could interfere on the operation of others cores since they share resources, such as memory and network bandwidth. A very aggressive prefetching of a core can overload the network connection, increasing the communication which delays the network requests, increasing the penalty in the processor. In this context, this paper presents a Balanced Prefetching Aggressiveness Controller for a multiprocessor platform that minimizes the processor penalty. We tested the proposed controller in a network-based multiprocessor based on the Sparc V8. The results show a reduction of up to 23% and 7% on average in the processor's penalty, 34% in the cache pollution on average, and increase of 30% on prefetching accuracy for concurrent applications when compared to a system with fixed prefetching aggressiveness approach.