Clock Distribution Area Reduction Using a Multiple-Valued Clocking Approach

Multi-phase clocking methods are well known and widely used in high-performance integrated circuit design. Such a scheme allows for relaxation of timing constraints among disjoint partitions of the logic circuitry since lower frequency local clocking is required as compared to the system clock frequency at the cost of increased clock distribution network area. The disadvantage is that multiple clock distribution trees are required, one for each clock domain or phase within the integrated circuit. Clock distribution networks have the highest fanout of any circuit within typical ICs and represent a significant amount of resource utilization. We devise a method that retains the advantages of multi-phase IC design, but utilizes a single global multiple-valued clock signal distribution network versus separate distribution networks for each phase in an ASIC or custom VLSI implementation. The technique requires a minimal amount of modification to existing multi-phase designs and is evaluated and compared to traditional multiphase designs. Furthermore, the approach is applicable to programmable logic (FPGA) implementations through distributing the multiple-valued clock signal using log 2 (N) distribution networks for an N-phase system. Experimental results are provided to validate and evaluate the approach.