Nonplanar VLSI device analysis using the solution of Poisson's equation

Techniques are presented for calculating the drain current of small-geometry MOSFET's in the linear, subthreshold, and punch-through regions of device operation. The current calculation depends only on the electrostatic solution of the two-dimensional Poisson equation in the device. The accuracy of the techniques is established by comparisons with full two-dimensional simulations based on the simultaneous solution of the Poisson and minority-carrier current-continuity equations. The results of simulation also agree well with measurements on MOSFET's having submicrometer effective channel lengths. The application of the simulations to nonplanar technologies is illustrated by the analysis of a taper-isolated dynamic-gain RAM cell. A description is given of simple numerical techniques for solving Poisson's equation in the presence of nonplanar boundaries. The solution method demonstrates good convergence characteristics and minimizes computer storage requirements. Consequently, the simulation capabilities have been successfully implemented on a desktop calculator (Hewlett-Packard 9845) and on minicomputers (Hewlett-Packard 2100 and 1000-F).

[1]  E. Demoulin,et al.  Process statistics of submicron MOSFET's , 1979, 1979 International Electron Devices Meeting.

[2]  D. W. Lucas,et al.  A numerical analysis of the d.c. performance of small geometry lateral transistors , 1974 .

[3]  T. Sudo,et al.  Two-dimensional semiconductor analysis using finite-element method , 1979, IEEE Transactions on Electron Devices.

[4]  L. D. Yau,et al.  A simple theory to predict the threshold voltage of short-channel IGFET's , 1974 .

[5]  H. Runge.  Distribution of implanted ions under arbitrarily shaped mask edges , 1977 .

[6]  M. Yamamoto,et al.  Submicron channel MOSFET's logic under punchthrough , 1978 .

[7]  F. D. L. Moneda.  Threshold voltage from numerical solution of the two-dimensional MOS transistor , 1973 .

[8]  B. A. Carré,et al.  The Determination of the Optimum Accelerating Factor for Successive Over-relaxation , 1961, Comput. J..

[9]  S.G. Chamberlain,et al.  A calibrated model for the subthreshold operation of a short channel MOSFET including surface states , 1979, IEEE Journal of Solid-State Circuits.

[10]  H. W. Loeb,et al.  Application of 2-dimensional solutions of the Shockley-Poisson equation to inversion-layer m.o.s.t. devices , 1968 .

[11]  A. Rusu,et al.  Deep-depletion breakdown voltage of silicon-dioxide/silicon MOS capacitors , 1979, IEEE Transactions on Electron Devices.

[12]  G. Haddad,et al.  Finite-element simulation of GaAs MESFET's with lateral doping profiles and submicron gates , 1976, IEEE Transactions on Electron Devices.

[13]  G.W. Taylor,et al.  Charge-coupled device structures for VLSI memories , 1979, IEEE Transactions on Electron Devices.

[14]  Gerhard K. Ackermann,et al.  Threshold voltage of narrow channel field effect transistors , 1976 .

[15]  G. Taylor.  Subthreshold conduction in MOSFET's , 1978, IEEE Transactions on Electron Devices.

[16]  W. Engl,et al.  Two-dimensional computer simulation for switching a bipolar transistor out of saturation , 1975, IEEE Transactions on Electron Devices.

[17]  K. H. Nicholas,et al.  A comparison of simple and numerical two-dimensional models for the threshold voltage of short channel MOSTs , 1977 .

[18]  R. Barsan.  Characteristics of the overlaid charge-coupled device , 1979, IEEE Transactions on Electron Devices.

[19]  G.W. Taylor,et al.  Taper isolated dynamic gain RAM cell , 1978, 1978 International Electron Devices Meeting.

[20]  C. Bulucea,et al.  Surface breakdown in silicon planar junctions—A computer-aided experimental determination of the critical field , 1974 .

[21]  R.H. Dennard,et al.  1 µm MOSFET VLSI technology: Part II—Device designs and characteristics for high-performance logic applications , 1979, IEEE Transactions on Electron Devices.

[22]  T. Toyabe,et al.  Analytical models of threshold voltage and breakdown voltage of short-channel MOSFET's derived from two-dimensional analysis , 1979, IEEE Transactions on Electron Devices.

[23]  R. Dutton,et al.  Models for computer simulation of complete IC fabrication process , 1979 .

[24]  Mietek Bakowski,et al.  Influence of bevel angle and surface charge on the breakdown voltage of negatively beveled diffused p-n junctions , 1975 .