ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power has become crucially important. ORION was amongst the first NoC power models released, and has since been fairly widely used for early-stage power estimation of NoCs. However, when validated against recent NoC prototypes - the Intel 80-core Teraflops chip and the Intel scalable communications core (SCC) chip - we saw significant deviation that can lead to erroneous NoC design choices. This prompted our development of ORION 2.0, an extensive enhancement of the original ORION models which includes completely new subcomponent power models, area models, as well as improved and updated technology models. Validation against the two Intel chips confirms a substantial improvement in accuracy over the original ORION. A case study with these power models plugged within the COSI-OCC NoC design space exploration tool confirms the need for, and value of, accurate early-stage NoC power estimation. To ensure the longevity of ORION 2.0, we will be releasing it wrapped within a semi-automated flow that automatically updates its models as new technology files become available.

[1]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[2]  Krste Asanovic,et al.  Replacing global wires with an on-chip network: a power analysis , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[3]  Kunle Olukotun,et al.  Niagara: a 32-way multithreaded Sparc processor , 2005, IEEE Micro.

[4]  Arnab Banerjee,et al.  A Power and Energy Exploration of Network-on-Chip Architectures , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[5]  Karam S. Chatha,et al.  A power and performance model for network-on-chip architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[6]  Diana Marculescu,et al.  System level power and performance modeling of GALS point-to-point communication interfaces , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[7]  Mahmut T. Kandemir,et al.  The design and use of simplePower: a cycle-accurate energy estimation tool , 2000, Proceedings 37th Design Automation Conference.

[8]  Vamsi Boppana,et al.  Accurate pre-layout estimation of standard cell characteristics , 2004, Proceedings. 41st Design Automation Conference, 2004..

[9]  S. Asano,et al.  The design and implementation of a first-generation CELL processor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[10]  A. Kumary,et al.  A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS , 2007 .

[11]  R. Passerone,et al.  System level design paradigms: Platform-based design and communication synthesis , 2004 .

[12]  Krste Asanovic,et al.  Power-optimal pipelining in deep submicron technology , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[13]  Gu-Yeon Wei,et al.  Process Variation Tolerant 3T1D-Based Cache Architectures , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[14]  Henry Hoffmann,et al.  The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs , 2002, IEEE Micro.

[15]  Li-Shiuan Peh,et al.  High-level power analysis for on-chip networks , 2004, CASES '04.

[16]  Niraj K. Jha,et al.  A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS , 2007, ICCD.

[17]  Li-Shiuan Peh,et al.  Polaris: A System-Level Roadmap for On-Chip Interconnection Networks , 2006, 2006 International Conference on Computer Design.

[18]  Norman P. Jouppi,et al.  Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0 , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[19]  Margaret Martonosi,et al.  Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data , 2003, MICRO.

[20]  Vittorio Zaccaria,et al.  System level power modeling and simulation of high-end industrial network-on-chip , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[21]  Shubha Bhat.  ENERGY MODELS FOR NETWORK-ON-CHIP COMPONENTS , 2005 .

[22]  Sriram R. Vangal,et al.  A 5-GHz Mesh Interconnect for a Teraflops Processor , 2007, IEEE Micro.

[23]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[24]  Li-Shiuan Peh,et al.  Leakage power modeling and optimization in interconnection networks , 2003, ISLPED '03.

[25]  Narayanan Vijaykrishnan,et al.  A clock power model to evaluate impact of architectural and technology optimizations , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[26]  Luca P. Carloni,et al.  Interconnect modeling for improved system-level design optimization , 2008, 2008 Asia and South Pacific Design Automation Conference.

[27]  Anthony Chun,et al.  Architecture of the Scalable Communications Core's Network on Chip , 2007, IEEE Micro.

[28]  Alberto L. Sangiovanni-Vincentelli,et al.  A Methodology and an Open Software Infrastructure for Constraint-Driven Synthesis of On-Chip Communications , 2007 .

[29]  Sudhakar Yalamanchili,et al.  Power constrained design of multiprocessor interconnection networks , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[30]  Henry Hoffmann,et al.  Evaluation of the Raw microprocessor: an exposed-wire-delay architecture for ILP and streams , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[31]  Sharad Malik,et al.  Orion: a power-performance simulator for interconnection networks , 2002, MICRO.