Impact of RTN and NBTI on Synchronous Circuit Reliability

We investigate a synchronous circuit reliability for 65nm−40nm CMOS technology. The impact of Random telegraph noise (RTN) and Negative Bias Temperature Instability (NBTI) on a circuit is evaluated. We found two things. (i) RTN at one or a few stages of a combinational circuit induces a large delay fluctuation under low voltage operation. (ii) LSI lifetime can be extended by utilizing NBTI recovery.