Security, Reliability and Test Aspects of the RISC-V Ecosystem

RISC-V has emerged as a viable solution on academia and industry. However, to use open source hardware for safety-critical applications, we need a deep understanding of the way in which well established mechanisms for testing and reliability could be integrated and deployed on the RISC-V ecosystem, and we need a clear knowledge on how such an ecosystem can be leveraged to improve security. This paper includes four contributions presenting the potential of RISC-V in security research, the way in which RISC-V can be hardened against power analysis attacks, how to implement, using RISC-V, software and hardware/software solutions for dual core lock step, and how to perform system-level testing in the RISC-V ecosystem.

[1]  Michael Hutter,et al.  Protecting RISC-V against Side-Channel Attacks , 2019, DAC.

[2]  Jaume Abella,et al.  Timely Error Detection for Effective Recovery in Light-Lockstep Automotive Systems , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Rahul Bodduna,et al.  PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance , 2020, 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[4]  Jaume Abella,et al.  SELENE: Self-Monitored Dependable Platform for High-Performance Safety-Critical Systems , 2020, 2020 23rd Euromicro Conference on Digital System Design (DSD).

[5]  Luca Benini,et al.  Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core , 2020, ArXiv.

[6]  Luis D. Rojas,et al.  Effectively Using Machine Learning to Expedite System Level Test Failure Debug , 2019, 2019 IEEE International Test Conference (ITC).

[7]  Adam M. Izraelevitz,et al.  The Rocket Chip Generator , 2016 .

[8]  Jaume Abella,et al.  Software-only based Diverse Redundancy for ASIL-D Automotive Applications on Embedded HPC Platforms , 2020, 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

[9]  Karine Heydemann,et al.  Custom Instruction Support for Modular Defense against Side-channel and Fault Attacks , 2020, IACR Cryptol. ePrint Arch..

[10]  Michael Hamburg,et al.  Meltdown: Reading Kernel Memory from User Space , 2018, USENIX Security Symposium.

[11]  Chester Rebeiro,et al.  SHAKTI-MS: a RISC-V processor for memory safety in C , 2019, LCTES.

[12]  Abubakr Abdulgadir,et al.  Vulnerability Analysis of a Soft Core Processor through Fine-grain Power Profiling , 2019, IACR Cryptol. ePrint Arch..

[13]  Stefan Mangard,et al.  Domain-Oriented Masking: Compact Masked Hardware Implementations with Arbitrary Protection Order , 2016, IACR Cryptol. ePrint Arch..

[14]  Thomas Unterluggauer,et al.  Concealing Secrets in Embedded Processors Designs , 2016, CARDIS.

[15]  Rainer Leupers,et al.  Direct FPGA-based power profiling for a RISC processor , 2015, 2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings.

[16]  Kostas Papagiannopoulos,et al.  Mind the Gap: Towards Secure 1st-Order Masking in Software , 2017, COSADE.

[17]  Luca Benini,et al.  Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Matthias Sauer,et al.  Exploring the Mysteries of System-Level Test , 2020, 2020 IEEE 29th Asian Test Symposium (ATS).

[19]  Siva Sai Yerubandi,et al.  Differential Power Analysis , 2002 .

[20]  Stefan Mangard,et al.  Protecting AES Software Implementations on 32-Bit Processors Against Power Analysis , 2007, ACNS.

[21]  Josep Balasch,et al.  On the Cost of Lazy Engineering for Masked Software Implementations , 2014, CARDIS.

[22]  Luca Benini,et al.  The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology , 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[23]  Michael Tunstall,et al.  On the Effect of the (Micro)Architecture on the Development of Side-Channel Resistant Software , 2020, IACR Cryptol. ePrint Arch..

[24]  Alessandro Barenghi,et al.  Side-channel security of superscalar CPUs : Evaluating the Impact of Micro-architectural Features , 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

[25]  P. Rohatgi,et al.  A testing methodology for side channel resistance , 2011 .

[26]  Johann Großschädl,et al.  Micro-Architectural Power Simulator for Leakage Assessment of Cryptographic Software on ARM Cortex-M3 Processors , 2018, IACR Cryptol. ePrint Arch..

[27]  Vincent Rijmen,et al.  Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches , 2011, Journal of Cryptology.

[28]  Mario Werner,et al.  Protecting RISC-V Processors against Physical Attacks , 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[29]  Harry H. Chen,et al.  Beyond structural test, the rising need for system-level test , 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

[30]  Michael Hamburg,et al.  Spectre Attacks: Exploiting Speculative Execution , 2018, 2019 IEEE Symposium on Security and Privacy (SP).

[31]  Adit D. Singh,et al.  An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures , 2019, 2019 IEEE International Test Conference (ITC).

[32]  M. Sonza Reorda,et al.  Applicative System Level Test introduction to Increase Confidence on Screening Quality , 2020, 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).