Modeling of PMOS NBTI Effect Considering Temperature Variation

Negative bias temperature instability (NBTI) has come to the forefront of critical reliability phenomena in advanced CMOS technology. In this paper, we propose a fast and accurate PMOS NBTI model, in which the temperature variation and the ratio of active to standby time are considered in both stress and relaxation phases. A PMOS Vth degradation model and a digital circuits' temporal performance degradation estimation method are developed based on our PMOS NBTI model. The simulation results show that: 1) our dynamic NBTI model without temperature variation is as accurate as previous models, the error is less than 2.3%; 2) the analysis error of PMOS Vth degradation may reach up to 52.6% without considering temperature variation; 3) for ISCAS85 benchmark circuits, the error of worst case performance degradation analysis is about on average 52.0%; 4) the ratio of active to standby time has a considerable impact during the performance degradation analysis

[1]  C.H. Kim,et al.  An Analytical Model for Negative Bias Temperature Instability , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[2]  Yu (Kevin) Cao,et al.  What is Predictive Technology Model (PTM)? , 2009, SIGD.

[3]  Yu Cao,et al.  Modeling and minimization of PMOS NBTI effect for robust nanometer design , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[4]  H. Miyake,et al.  Mechanism of Dynamic Bias Temperature Instability in p- and nMOSFETs: The Effect of Pulse Waveform , 2006, IEEE Transactions on Electron Devices.

[5]  Srikanth Krishnan,et al.  Impact of negative bias temperature instability on digital circuit reliability , 2005, Microelectron. Reliab..

[6]  Laura Peters.  NBTI: A growing threat to device reliability , 2004 .

[7]  Sani R. Nassif,et al.  High Performance CMOS Variability in the 65nm Regime and Beyond , 2006, 2007 IEEE International Electron Devices Meeting.

[8]  B.C. Paul,et al.  Impact of NBTI on the temporal performance degradation of digital circuits , 2005, IEEE Electron Device Letters.

[9]  Muhammad Ashraful Alam,et al.  A comprehensive model of PMOS NBTI degradation , 2005, Microelectron. Reliab..

[10]  Ogawa,et al.  Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si-SiO2 interface. , 1995, Physical review. B, Condensed matter.

[11]  Sachin S. Sapatnekar,et al.  Impact of NBTI on SRAM read stability and design for reliability , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[12]  James H. Stathis,et al.  The negative bias temperature instability in MOS devices: A review , 2006, Microelectron. Reliab..

[13]  S. Mahapatra,et al.  On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress , 2006, IEEE Transactions on Electron Devices.

[14]  S. Selberherr,et al.  Impact of NBTI-driven parameter degradation on lifetime of a 90nm p-MOSFET , 2005, 2005 IEEE International Integrated Reliability Workshop.

[15]  M.A. Alam,et al.  Mechanism of negative bias temperature instability in CMOS devices: degradation, recovery and impact of nitrogen , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[16]  Kaushik Roy,et al.  Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[17]  M. Denais,et al.  NBTI degradation: From physical mechanisms to modelling , 2006, Microelectron. Reliab..