A 0.6V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ΔΣ LDO and temperature compensation circuits in 65nm CMOS

This paper presents an ultra-low voltage and ultra-low power PVT tolerant digital PLL with a semi-digital low dropout regulator (LDO). A low cost integrated temperature compensation circuit (TCC) is proposed and implemented by combining with a proposed ΑΣ LDO to reduce temperature variation of the digitally-controlled relaxation oscillator (DCRXO). A 50-to-145MHz PLL implemented in 65nm CMOS consumes a 77.3μW from a 0.6V supply at 100MHz output and achieves the phase noise of −94.3dBc/Hz at 1MHz offset frequency and the reference spur below −70dBc at 6.25MHz offset frequency. The output frequency variation of open-loop oscillator with the TCC is less than 5% across temperature variation from −20° C to 90° C.

[1]  Ping-Ying Wang,et al.  15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[2]  Arijit Raychowdhury,et al.  5.6 A 0.13μm fully digital low-dropout regulator with adaptive control and reduced dynamic stability for ultra-wide dynamic range , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[3]  Edoardo Charbon,et al.  IEEE Custom Integrated Circuits Conference (CICC) , 2009, CICC 2009.

[4]  Yingchieh Ho,et al.  A Near-Threshold 480 MHz 78 µW All-Digital PLL With a Bootstrapped DCO , 2013, IEEE Journal of Solid-State Circuits.

[5]  Byunghoo Jung,et al.  A 0.5-V, 440-µW Frequency Synthesizer for Implantable Medical Devices , 2011, IEEE Journal of Solid-State Circuits.

[6]  Jen-Chieh Liu,et al.  A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  Taeik Kim,et al.  15.2 A 0.012mm2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[8]  Dae Hyun Kwon,et al.  A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation , 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

[9]  Amr Elshazly,et al.  A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration , 2011, IEEE Journal of Solid-State Circuits.

[10]  Zhihua Wang,et al.  A 0.35–0.5-V 18–152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  Taeik Kim,et al.  A 0.55V 100MHz ADPLL with ΔΣ LDO and Relaxation DCO in 65nm CMOS , 2015, 2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT).