PLL Real Number Modeling in SystemVerilog
暂无分享,去创建一个
[1] Jingchang Nan,et al. Design of PLL behavioral model based on the Verilog-A , 2011, 2011 4th IEEE International Symposium on Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications.
[2] Mark Horowitz,et al. A Verilog piecewise-linear analog behavior model for mixed-signal validation , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.
[3] Liu Lian-xi,et al. Design of PLL system based Verilog-AMS behavior models , 2005, Proceedings of 2005 IEEE International Workshop on VLSI Design and Video Technology, 2005..
[4] ByongChan Lim,et al. Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.
[5] Soner Yaldiz,et al. A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology , 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).
[6] Behzad Razavi,et al. RF Microelectronics , 1997 .
[7] Nikolaos Georgoulopoulos,et al. Real number modeling of a flash ADC using SystemVerilog , 2017, 2017 Panhellenic Conference on Electronics and Telecommunications (PACET).