PLL Real Number Modeling in SystemVerilog

This paper discusses different techniques for the development of event-driven, analog functional models based on System Verilog for system-level verification. It leverages the recent introduction of additional real number capabilities in System Verilog to represent analog signals, known by Real Number Modeling (RNM). In addition to the introduction of composite user-defined net types that can carry multiple information, e.g. voltage, current, impedance,…. A Phase Locked Loop (PLL) model is considered as a vehicle to demonstrate the different proposed techniques. It is shown that using a pure System Verilog model, it is possible to achieve a comparable accuracy to Spice transistor-level simulation with a 27x simulation speedup.