A 250-MHz wave pipelined adder in 2-/spl mu/m CMOS

Wave pipelining (also known as maximal rate pipelining) is a timing methodology used in digital systems to increase the number of effective pipelined stages without increasing the number of physical registers in the system. Using this technique, new data are applied to the inputs of a combinational block before the previous outputs are available, thus effectively pipelining the combinational logic. Achieving a high degree of wave pipelining in CMOS technology requires careful study of delay balancing technique involving circuit design, layout method, and testing structure. A 16-b parallel adder, utilizing wave pipelining is implemented with MOSIS 2-/spl mu/m technology and test results of fabricated devices show more than nine times speedup over nonpipelined operation. >

[1]  Peter M. Kogge,et al.  The Architecture of Pipelined Computers , 1981 .

[2]  Derek Chi-Lan Wong.  Techniques for designing high-performance digital circuits using wave pipelining , 1992 .

[3]  Wayne Burleson,et al.  Wave-domino logic: theory and applications , 1995 .

[4]  Michael J. Flynn,et al.  A bipolar population counter using wave pipelining to achieve 2.5* normal clock frequency , 1992 .

[5]  Bradley Kevin Fawcett.  Maximal Clocking Rates for Pipelined Digital Systems , 1975 .

[6]  Wentai Liu,et al.  Theoretical and Practical Issues in CMOS Wave Pipelining , 1991, VLSI.

[7]  H. T. Kung,et al.  A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.

[8]  R. K. Brayton,et al.  Valid clocking in wavepipelined circuits , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[9]  Wentai Liu,et al.  A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution , 1994 .

[10]  S. F. Anderson,et al.  The IBM system/360 model 91: floating-point execution unit , 1967 .

[11]  Maciej J. Ciesielski,et al.  Clock period minimization with wave pipelining , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Kurt Antreich,et al.  Accelerated Fault Simulation and Fault Grading in Combinational Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  John P. Fishburn,et al.  Clock Skew Optimization , 1990, IEEE Trans. Computers.

[14]  Giovanni De Micheli,et al.  Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  L. W. Cotten.  Maximum-rate pipeline systems , 1969, AFIPS '69 (Spring).