Evaluation of a New Platform For Image Filter Evolution

This paper describes a new FPGA implementation of a system for evolutionary image filter design. Three parallel search algorithms are compared. An optimal mutation rate and the quality of three pseudo-random number generators are investigated. The efficiency of proposed system is demonstrated on the problem of removing the salt-and- pepper noise with intensity of 5%, 10% and 20% and designing an edge detector which works with input images corrupted by the salt-and-pepper noise.

[1]  Gunnar Tufte,et al.  Evolving an adaptive digital filter , 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.

[2]  Lukas Sekanina,et al.  An evolvable hardware system in Xilinx Virtex II Pro FPGA , 2007 .

[3]  J. Raja Paul Perinbam,et al.  Digital image filter design using evolvable hardware , 2005, Fourth Annual ACIS International Conference on Computer and Information Science (ICIS'05).

[4]  Andres Upegui,et al.  Evolving Hardware with Self-reconfigurable connectivity in Xilinx FPGAs , 2006, First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06).

[5]  James A. Foster,et al.  Special Purpose Image Convolution with Evolvable Hardware , 2000, EvoWorkshops.

[6]  Yang Zhang,et al.  Digital circuit design using intrinsic evolvable hardware , 2004, Proceedings. 2004 NASA/DoD Conference on Evolvable Hardware, 2004..

[7]  Takuji Nishimura,et al.  Mersenne twister: a 623-dimensionally equidistributed uniform pseudo-random number generator , 1998, TOMC.

[8]  Tughrul Arslan,et al.  Evolvable Components—From Theory to Hardware Implementations , 2005, Genetic Programming and Evolvable Machines.

[9]  Lukás Sekanina,et al.  Image Filter Design with Evolvable Hardware , 2002, EvoWorkshops.

[10]  Kyrre Glette,et al.  A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device , 2005, ICES.

[11]  Lukás Sekanina,et al.  An Evolvable Image Filter: Experimental Evaluation of a Complete Hardware Implementation in FPGA , 2005, ICES.

[12]  Paul J. Layzell,et al.  Explorations in design space: unconventional electronics design through artificial evolution , 1999, IEEE Trans. Evol. Comput..

[13]  David A. Gwaltney,et al.  A VHDL core for intrinsic evolution of discrete time filters with signal feedback , 2005, 2005 NASA/DoD Conference on Evolvable Hardware (EH'05).

[14]  Andreas Tockhorn,et al.  Rapid Evolution of Time-Efficient Packet Classifiers , 2006, 2006 IEEE International Conference on Evolutionary Computation.