论文信息 - FPGA Implementation of Deep Neural Network Based Equalizers for High-Speed PON

FPGA Implementation of Deep Neural Network Based Equalizers for High-Speed PON

A fixed-point deep neural network-based equalizer is implemented in FPGA and is shown to outperform MLSE in receiver sensitivity for 50 Gb/s PON downstream link. Embedded parallelization is proposed and verified to reduce hardware resources.

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