A Switching Activity Analysis and visualisation tool for power optimisation of SoC buses
暂无分享,去创建一个
[1] Naresh R. Shanbhag,et al. Coding for systern-on-chip networks: a unified framework , 2004, Proceedings. 41st Design Automation Conference, 2004..
[2] Naresh R. Shanbhag,et al. A coding framework for low-power address and data busses , 1999, IEEE Trans. Very Large Scale Integr. Syst..
[3] Jan M. Rabaey,et al. Architectural power analysis: The dual bit type method , 1995, IEEE Trans. Very Large Scale Integr. Syst..
[4] Mircea R. Stan,et al. Bus-invert coding for low-power I/O , 1995, IEEE Trans. Very Large Scale Integr. Syst..
[5] M.A. Elgamel,et al. Interconnect noise analysis and optimization in deep submicron technology , 2003, IEEE Circuits and Systems Magazine.
[6] A. Chandrakasan,et al. Transition pattern coding: An approach to reduce energy in interconnect , 2000, Proceedings of the 26th European Solid-State Circuits Conference.
[7] E. Macii,et al. Low-Power EDA Technologies: State-of-the-Art and Beyond , 2006, 2006 Advanced Signal Processing, Circuit and System Design Techniques for Communications.
[8] Tomás Lang,et al. Exploiting the locality of memory references to reduce the address bus energy , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.
[9] Paul Fugger. Rtl-based signal statistics calculation facilitates low power design approaches , 2003 .
[10] Jacob L fvenberg. Non-Redundant Coding for Deep Sub-Micron Address Buses , 2004 .
[11] Paul-Peter Sotiriadis,et al. Interconnect modeling and optimization in deep sub-micron technologies , 2002 .
[12] Luca Benini,et al. Reducing power consumption of dedicated processors through instruction set encoding , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).
[13] Jacob Löfvenberg. Non-redundant coding for deep sub-micron address buses , 2004 .