Refinement-Based Modeling of 3D NoCs

Three-dimensional Networks-on-Chip (3D NoC) have recently emerged essentially via the stacking of multiple layers of two-dimensional NoCs. The resulting structures can support a very high level of parallelism for both communication and computation as well as higher speeds, at the cost of increased complexity. To address the potential problems due to the highly complex NoCs, we study them with formal methods. In particular, we base our study on the refinement relation between models of the same system. We propose three abstract models of 3D NoCs, M0, M1, and M2 so that M0 ⊑ M1 ⊑ M2, where ''' denotes the refinement relation. Each of these models provides templates for communication constraints and guarantees the communication correctness. We then show how to employ one of these models for reasoning about the communication correctness of the XYZ-routing algorithm.

[1]  Partha Pratim Pande,et al.  Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation , 2009, IEEE Transactions on Computers.

[2]  Kaisa Sere,et al.  Superposition refinement of reactive systems , 2005, Formal Aspects of Computing.

[3]  Chita R. Das,et al.  MIRA: A Multi-layered On-Chip Interconnect Router Architecture , 2008, 2008 International Symposium on Computer Architecture.

[4]  Laurence Pierre,et al.  A Formal Approach to the Verification of Networks on Chip , 2009, EURASIP J. Embed. Syst..

[5]  Natalie D. Enright Jerger,et al.  Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support , 2008, 2008 International Symposium on Computer Architecture.

[6]  Michael Kishinevsky,et al.  Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs , 2004, FMCAD.

[7]  Axel Jantsch,et al.  Connection-oriented multicasting in wormhole-switched networks on chip , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[8]  Partha Pratim Pande,et al.  A scalable communication-centric SoC interconnect architecture , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

[9]  Jean-Raymond Abrial,et al.  Refinement, Decomposition, and Instantiation of Discrete Models: Application to Event-B , 2007, Fundam. Informaticae.

[10]  Jean-Raymond Abrial.  A System Development Process with Event-B and the Rodin Platform , 2007, ICFEM.

[11]  Anna Slobodová,et al.  Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation , 2009, CAV.

[12]  Ajitha Rajan,et al.  Requirements Coverage as an Adequacy Measure for Conformance Testing , 2008, ICFEM.

[13]  Dominique Cansell,et al.  Refinement and Reachability in EventB , 2005, ZB.

[14]  Jean-Raymond Abrial,et al.  Modeling in event-b - system and software engineering by Jean-Raymond Abrial , 2010, SOEN.

[15]  Hiroki Matsutani,et al.  Balanced Dimension-Order Routing for k-ary n-cubes , 2009, 2009 International Conference on Parallel Processing Workshops.

[16]  Shmuel Katz,et al.  A superimposition control construct for distributed systems , 1993, TOPL.

[17]  Dakun Zhang,et al.  A Condition of Deadlock-Free Routing in Mesh Network , 2009, 2009 Second International Conference on Intelligent Networks and Intelligent Systems.

[18]  John Harrison.  Formal verification at Intel , 2003, 18th Annual IEEE Symposium of Logic in Computer Science, 2003. Proceedings..

[19]  Sandeep K. Shukla,et al.  Formal methods and models for system design: a system level perspective , 2004 .

[20]  Leonidas Tsiopoulos,et al.  Formal Development of NoC Systems in B , 2006, Nord. J. Comput..

[21]  Hamid Sarbazi-Azad,et al.  XMulator: A Listener-Based Integrated Simulation Platform for Interconnection Networks , 2007, First Asia International Conference on Modelling & Simulation (AMS'07).

[22]  Sandeep K. Shukla,et al.  Formal Methods and Models for System Design , 2004, Springer US.

[23]  Jean-Raymond Abrial,et al.  The B-book - assigning programs to meanings , 1996 .

[24]  Luca Benini,et al.  An efficient distributed memory interface for many-core platform with 3D stacked DRAM , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[25]  Yong-Bin Kim,et al.  Fault Tolerant Source Routing for Network-on-chip , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

[26]  Bill Lin,et al.  Design of Application-Specific 3D Networks-on-Chip Architectures , 2011, 3D Integration for NoC-based SoC Architectures.

[27]  Hannu Tenhunen,et al.  HAMUM - A Novel Routing Protocol for Unicast and Multicast Traffic in MPSoCs , 2010, 2010 18th Euromicro Conference on Parallel, Distributed and Network-based Processing.

[28]  Shashi Kumar,et al.  Slack-time aware routing in NoC systems , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[29]  Kaisa Sere,et al.  Stepwise Refinement of Action Systems , 1991, Struct. Program..

[30]  Vincenzo Catania,et al.  Application Specific Routing Algorithms for Networks on Chip , 2009, IEEE Transactions on Parallel and Distributed Systems.