Optimization Methods in Look-Up Table Rings

A Look-Up Table (LUT) ring consists of memories, programmable interconnections and a control circuit. It sequentially emulates an LUT cascade representing a multipleoutput logic function. In this paper, we consider the realization of multi-output functions with LUT rings using large memories. In contrast to previous approaches where the number of inputs to each LUT cell is fixed, we allow the number of inputs to be different for each cell. With this new approach, we can reduce the number of levels and the total amount of memory by selecting the optimal size for each cell and by packing the memory. We have developed an optimization system for LUT ring designs using dynamic programming. In trials, our system was able to reduce the amount of memory required for some designs by as much as 60%.

[1]  Munehiro Matsuura,et al.  A method to decompose multiple-output logic functions , 2004, Proceedings. 41st Design Automation Conference, 2004..

[2]  Robert K. Brayton.  The future of logic synthesis and verification , 2001 .

[3]  Rajeev Murgai,et al.  Logic synthesis for a single large look-up table , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[4]  Tsutomu Sasao,et al.  Implementation of multiple-output functions using PQMDDs , 2000, Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000).

[5]  Tsutomu Sasao,et al.  A hardware simulation engine based on decision diagrams , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

[6]  Tsutomu Sasao.  A cascade realization of multiple-output function for reconfigurable hardware , 2001 .

[7]  Tsutomu Sasao,et al.  Switching Theory for Logic Synthesis , 1999, Springer US.