Locality and Singularity for Store-Atomic Memory Models

Robustness is a correctness notion for concurrent programs running under relaxed consistency models. The task is to check that the relaxed behavior coincides (up to traces) with sequential consistency (SC). Although computationally simple on paper (robustness has been shown to be PSPACE-complete for TSO, PGAS, and Power), building a practical robustness checker remains a challenge. The problem is that the various relaxations lead to a dramatic number of computations, only few of which violate robustness.

[1]  Katherine Yelick,et al.  Titanium Language Reference Manual (Version 2.20) , 2006 .

[2]  Katherine Yelick,et al.  Titanium Language Reference Manual , 2001 .

[3]  Robert W. Numrich,et al.  Co-array Fortran for parallel programming , 1998, FORF.

[4]  Leslie Lamport,et al.  Time, clocks, and the ordering of events in a distributed system , 1978, CACM.

[5]  Francesco Zappa Nardelli,et al.  x86-TSO , 2010, Commun. ACM.

[6]  Eran Yahav,et al.  Effective Abstractions for Verification under Relaxed Memory Models , 2015, VMCAI.

[7]  Satish Narayanasamy,et al.  A case for an SC-preserving compiler , 2011, PLDI '11.

[8]  Roland Meyer,et al.  Robustness against Power is PSpace-complete , 2014, ICALP.

[9]  Rupak Majumdar,et al.  A Theory of Partitioned Global Address Spaces , 2013, FSTTCS.

[10]  Sebastian Burckhardt,et al.  CheckFence: checking consistency of concurrent data types on relaxed memory models , 2007, PLDI '07.

[11]  Roland Meyer,et al.  Lazy TSO Reachability , 2015, FASE.

[12]  Barbara M. Chapman,et al.  Introducing OpenSHMEM: SHMEM for the PGAS community , 2010, PGAS '10.

[13]  Daniel Kroening,et al.  Software Verification for Weak Memory via Program Transformation , 2012, ESOP.

[14]  Mohamed Faouzi Atig,et al.  Getting Rid of Store-Buffers in TSO Analysis , 2011, CAV.

[15]  Dennis Shasha,et al.  Efficient and correct execution of parallel programs that share memory , 1988, TOPL.

[16]  Rui Machado,et al.  The Fraunhofer virtual machine: a communication library and runtime system based on the RDMA model , 2009, Computer Science - Research and Development.

[17]  Daniel Kroening,et al.  Don’t Sit on the Fence , 2013, ACM Trans. Program. Lang. Syst..

[18]  Jade Alglave,et al.  Understanding POWER multiprocessors , 2011, PLDI '11.

[19]  David L Weaver,et al.  The SPARC architecture manual : version 9 , 1994 .

[20]  Dan Bonachea GASNet Specification, v1.1 , 2002 .

[21]  Sebastian Burckhardt,et al.  What's Decidable about Weak Memory Models? , 2012, ESOP.

[22]  Leslie Lamport,et al.  How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs , 2016, IEEE Transactions on Computers.

[23]  Viktor Vafeiadis,et al.  Verifying Fence Elimination Optimisations , 2011, SAS.

[24]  Eran Yahav,et al.  Automatic inference of memory fences , 2010, Formal Methods in Computer Aided Design.

[25]  Roland Meyer,et al.  Checking and Enforcing Robustness against TSO , 2013, ESOP.

[26]  Jade Alglave,et al.  Stability in Weak Memory Models , 2011, CAV.

[27]  Satish Narayanasamy,et al.  End-to-end sequential consistency , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).

[28]  Bryan Carpenter,et al.  ARMCI: A Portable Remote Memory Copy Libray for Ditributed Array Libraries and Compiler Run-Time Systems , 1999, IPPS/SPDP Workshops.

[29]  Sebastian Burckhardt,et al.  Bounded Model Checking of Concurrent Data Types on Relaxed Memory Models: A Case Study , 2006, CAV.

[30]  Eran Yahav,et al.  Partial-coherence abstractions for relaxed memory models , 2011, PLDI '11.

[31]  Sebastian Burckhardt,et al.  Effective Program Verification for Relaxed Memory Models , 2008, CAV.

[32]  Katherine Yelick,et al.  Titanium Language Reference Manual, version 2.19 , 2005 .

[33]  Jade Alglave,et al.  Fences in Weak Memory Models , 2010, CAV.

[34]  Roland Meyer,et al.  Deciding Robustness against Total Store Ordering , 2011, ICALP.

[35]  Eran Yahav,et al.  Synthesis of Memory Fences via Refinement Propagation , 2014, SAS.

[36]  Parosh Aziz Abdulla,et al.  The Best of Both Worlds: Trading Efficiency and Optimality in Fence Insertion for TSO , 2015, ESOP.

[37]  Daniel Kroening,et al.  Partial Orders for Efficient Bounded Model Checking of Concurrent Software , 2013, CAV.

[38]  Parosh Aziz Abdulla,et al.  Counter-Example Guided Fence Insertion under TSO , 2012, TACAS.

[39]  Koushik Sen,et al.  Sound and Complete Monitoring of Sequential Consistency for Relaxed Memory Models , 2011, TACAS.

[40]  Jaejin Lee,et al.  Automatic fence insertion for shared memory multiprocessing , 2003, ICS '03.