Silicon Evaluation of Cell-Aware ATPG Tests and Small Delay Tests

This paper presents silicon results for two such proposed fault models: the cell aware fault model and the small delay defect fault model. The corresponding tests including cell-aware ATPG tests and Fast-than at-speed TDF tests are evaluated on an industrial design. Results from a high volume manufacturing experiment on a 65nm Serial Attached SCSI (SAS) RAID-On-a-Chip (ROC) device are presented. The incremental value of these fault models and tests beyond our current test flow is discussed.

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