A Graph Theoretic Approach to Partial Scan Design by K-Cycle Elimination

One method of reducing the difficulty of test generation for sequential circuits is by the use of full scan design. To overcome the large extra hardware overhead attendant in the full scan design, the concept of partial scan design has emerged with the virtue of less area and testability close to full scan. With the sequential circuit modeled as a directed graph, much effort has been expended by many authors to remove the subset of vertices representing Flip-Flops (FFs). First we introduce an efficient algorithm to find a Minimum Feedback Vertex Set (MFVS). Then cycles whose length are greater than Ii are removed under the observation that the complexity of test generation in sequential circuits may be caused by the lengthy cycles (long synchronization sequence). By providing different MFVSs with the same cardinality as well as K-cycle Feedback Vertex Sets, we allow designers to have choices which can minimize area and delay overhead. Experimental results show the effectiveness of these techniques.