A practical and efficient method for compare-point matching

An important step in using combinational equivalence checkers to verify sequential designs is identifying and matching corresponding compare-points in the two sequential designs to be verified. Both non-function and function-based matching methods are usually employed in commercial verification tools. In this paper, we describe a heuristic algorithm using ATPG for matching compare-points based on the functionality of the combinational blocks in the sequential designs. Results on industrial-sized circuits show our methods are both practical and efficient.

[1]  D. Brand.  Verification of large synthesized designs , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[2]  C.A.J. van Eijk,et al.  Detection of equivalent state variables in finite state machine verification , 1995 .

[3]  Thomas Filkorn,et al.  Symbolische Methoden für die Verifikation endlicher Zustandssysteme , 1992 .

[4]  J.R. Burch,et al.  Robust latch mapping for combinational equivalence checking , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[5]  Shi-Yu Huang,et al.  An ATPG-based framework for verifying sequential equivalence , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[6]  Dhiraj K. Pradhan,et al.  Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment , 1995, 32nd Design Automation Conference.

[7]  A. Kuehlmann,et al.  Equivalence Checking Using Cuts And Heaps , 1997, Proceedings of the 34th Design Automation Conference.