Ultra High-Speed and Low-Power Flexible Architecture using State Transition Matrix Model for EPC Gen-2 Communication Protocol Processor

Abstract In modern electronics, communication between systems is progressing towards wireless technology [1]. The rapid adaptation of the Wi-Fi technology across the world is a good example of the trends to come [2]. The IEEE 802.11 protocol [3], with its different layers of communication (information transfer), is obviously not ideal for applications that are time and energy sensitive. The EPCglobal Class-1 Generation-2 Protocol [4] (adapted by the International Organization for standards as the ISO 18000-6 [5]) is an impressive alternative that is slowly gaining global recognition as not just an RFID protocol, as it was primarily intended for, but as a front-end (communication link) for several identification and sensor applications [6]. This paper reports the design of a low-power processor specific for the Gen-2 instruction set with high emphasis on speed optimization at low power consumption. A novel approach in processor design as an asynchronous state machine is introduced, making the architecture extremely flexible and adaptable to changes in the protocol. Given that the full Gen-2 state transition matrix is available with direct linkage to the published standard, changes in the protocol can be directly effected through this matrix. Thus, the generation or the original and updated VLSI chips with the design flow disclosed is simply a matter of using the original or updated matrix. The design of the processor from a hardware description language (VHDL) level makes the final implementation possible either as an ASIC or on a suitable FPGA. The ASIC design flow is considered in this paper reporting the three fundamental characteristics—speed, power and area, of the post layout design. Industry standard Mentor Graphics ModelSim SE, Synopsys Design Compiler and Cadence Encounter are used in this research.