论文信息 - Clock jitter in direct RF and IF sampling wireless receivers

Clock jitter in direct RF and IF sampling wireless receivers

The effect of clock jitter on sampling systems is investigated. Analytical expressions are derived for the signal-to-noise ratio (SNR) of an ideal analogue-to-digital converter (ADC). The SNR expressions are based on the autocorrelation function properties of stationary random signals. The power spectral density (PSD) of the analysed signals is baseband/bandpass rectangular and bandpass raised cosine. System level simulations show that the SNR depends on the signal frequency rather than the bandwidth for direct RF and IF sampling. Special focus is given to direct sampling systems with raised cosine PSD (IS-95) in the presence of a blocking signal.

Jim S. Wight | T. Chalvatzis | E. Gagnon

[1] Andreas Wiesbauer,et al. On the jitter requirements of the sampling clock for analog-to-digital converters , 2002 .

[2] B. Liu. Timing jitter in digital filtering of analog signals , 1975 .

[3] Y. Akazawa,et al. Jitter analysis of high-speed sampling systems , 1990 .

[4] A. V. Balakrishnan,et al. On the problem of time jitter in sampling , 1962, IRE Trans. Inf. Theory.