Yield modeling for majority voting based defect-tolerant VLSI circuits

A yield model is developed for generalized N-tuple modular redundancy (NMR) based defect-tolerant designs. The yield model is both mathematical and simulation based where the simulation portion uses a random multiple fault injection simulation procedure while the mathematical portion accounts for defect clustering in the fabrication process. Analysis of the yield model and comparison with empirical data from actual wafer fabrications shows the model to be accurate. The NMR based approach to defect-tolerance in VLSI designs is most practical for application in gate arrays and pad-limited full and semi-custom VLSI.

[1]  Charles E. Stroud.  Reliability of majority voting based VLSI fault-tolerant circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[2]  C. H. Stapper,et al.  On yield, fault distributions, and clustering of particles , 1986 .

[3]  Charles H. Stapper.  Yield Model for Fault Clusters Within Integrated Circuits , 1984, IBM J. Res. Dev..

[4]  Charles E. Stroud,et al.  Applying built-in self-test to majority voting fault tolerant circuits , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[5]  Anthony S. Wojcik,et al.  A General, Constructive Approach to Fault-Tolerant Design Using Redundancy , 1989, IEEE Trans. Computers.

[6]  S.K. Tewksbury,et al.  Wafer level system integration: a review , 1989, IEEE Circuits and Devices Magazine.

[7]  Daniel P. Siewiorek.  Reliability Modeling of Compensating Module Failures in Majority Voted Redundancy , 1975, IEEE Transactions on Computers.

[8]  Charles E. Stroud,et al.  Multiple fault simulation with random and clustered fault injection , 1995, Proceedings of Eighth International Application Specific Integrated Circuits Conference.