Real time on-chip characterization of time delay arising from multi-level-metallization: decoupling of pure charging and drift-and-charging

Time delay, /spl tau//sub D/ due to MLM is systematically characterized in circuit operating conditions. Novel utilization of simple test patterns is shown to enable: (a) separation of pure charging and drift-and-charging contributions to /spl tau//sub D/, hence, (b) fast and accurate quantification of /spl tau//sub D/ in the limit of superconducting metal lines or low temperature operation, and (c) dynamic extraction of MLM parameters and their contribution to /spl tau//sub D/.