Real time on-chip characterization of time delay arising from multi-level-metallization: decoupling of pure charging and drift-and-charging
暂无分享,去创建一个
Jeong-Mo Hwang | Dae-Mann Kim | Young-Jong Lee | Dae-Gwan Kang | Hi-Deok Lee | H. Lee | Jeong-Mo Hwang | D. Kang | Myoung-Jun Jang | D. Kim | M. Jang | Youngjong Lee
[1] M. Bohr. Interconnect scaling-the real limiter to high performance ULSI , 1995, Proceedings of International Electron Devices Meeting.
[2] Keh-Jeng Chang,et al. 2001 needs for multi-level interconnect technology , 1995 .
[3] Yamashita,et al. Interconnect Scaling Scenario Using A Chip Level Interconnect Model , 1997, 1997 Symposium on VLSI Technology.
[4] Jeong-Mo Hwang,et al. Accurate extraction of reverse leakage current components of shallow silicided p/sup +/-n junction for quarter- and sub-quarter-micron MOSFET's , 1998 .