A novel efficient TSV built-in test for stacked 3D ICs

Abstract: A through-silicon via (TSV) is established as the main enabler for a three-dimensional integrated circuit (3D IC) that increases system density and compactness. The exponential increase in TSV density led to TSV-induced catastrophic and parametric faults. We propose an original architecture that detects errors caused by TSV manufacturing defects. The proposed design for testability is a built-in technique that detects errors in an early manufacturing stage and is hence very economically attractive. The proposal is capable of testing each and every TSV in the network. The technique achieves high fault coverage and high observability.

[1]  Daniel Arumí,et al.  Post-bond test of Through-Silicon Vias with open defects , 2014, 2014 19th IEEE European Test Symposium (ETS).

[2]  Alkis A. Hatzopoulos,et al.  Oscillation-based technique for TSV post-bond test considerations , 2017, 2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST).

[3]  Ding-Ming Kwai,et al.  A built-in self-test scheme for the post-bond test of TSVs in 3D ICs , 2011, 29th VLSI Test Symposium.

[4]  Vladimir Pasca,et al.  Développement d'architectures HW/SW tolérantes aux fautes et auto-calibrantes pour les technologies Intégrées 3D , 2013 .

[5]  Hsien-Hsin S. Lee,et al.  Test Challenges for 3D Integrated Circuits , 2009, IEEE Design & Test of Computers.

[6]  Mario H. Konijnenburg,et al.  A structured and scalable test access architecture for TSV-based 3D stacked ICs , 2010, 2010 28th VLSI Test Symposium (VTS).

[7]  Erik Jan Marinissen.  Challenges in testing TSV-based 3D stacked ICs: Test flows, test contents, and test access , 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

[8]  Fangming Ye,et al.  TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[9]  Badi.  A Novel Iddq Scanning Technique For Pre-Bond Testing , 2016 .

[10]  Shi-Yu Huang,et al.  Pre-Bond and Post-Bond Testing of TSVs and Die-to-Die Interconnects , 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

[11]  Robert Patti.  Homogeneous 3D Integration , 2011 .

[12]  Dean Malta,et al.  TSV Formation Overview , 2014 .

[13]  Tai-Hong Chen,et al.  Electromigration in Ni/Sn intermetallic micro bump joint for 3D IC chip stacking , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[14]  Sung Kyu Lim,et al.  Pre-Bond and Post-Bond Test and Signal Recovery Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3-D System , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[15]  Hung Viet Nguyen,et al.  Performance and power analysis of through silicon via based 3D IC integration , 2011, SLIP '11.

[16]  Sesh Ramaswami.  TSV Unit Processes and Integration , 2014 .

[17]  Andreas Herkersdorf,et al.  TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs , 2012, 2012 15th Euromicro Conference on Digital System Design.