HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications

This paper proposes a cost-effective, high-impedance-state (HIS)-insensitive, triple-node-upset (TNU)-tolerant and single-event-transient (SET)-filterable latch, namely HITTSFL, to ensure high reliability with low-cost. The latch mainly comprises an output-level SET-filterable Schmitt-trigger and three inverters that make the values stored in three parallel single-node-upset (SNU)-recoverable dual-interlocked-storage-cells (DICEs) converge at a common node to tolerate any possible TNU. The latch does not use C-elements to be insensitive to the HIS. Simulation results demonstrate the TNU-tolerability and SET-filterability of the proposed HITTSFL latch. Moreover, due to the use of clock-gating technologies and fewer transistors, the proposed latch can reduce delay, power, and area by 76.65%, 6.16%, and 28.55%, respectively, compared with the state-of-the-art TNU hardened latch (TNUHL) that cannot filter SETs.

[1]  Christos A. Papachristou,et al.  A low power memory cell design for SEU protection against radiation effects , 2012, 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[2]  Ronald F. DeMara,et al.  Design and Evaluation of DNU-Tolerant Registers for Resilient Architectural State Storage , 2019, ACM Great Lakes Symposium on VLSI.

[3]  Santosh Kumar Vishvakarma,et al.  Stable, Reliable, and Bit-Interleaving 12T SRAM for Space Applications: A Device Circuit Co-Design , 2017, IEEE Transactions on Semiconductor Manufacturing.

[4]  K. Kobayashi,et al.  A low-power and area-efficient radiation-hard redundant flip-flop, DICE ACFF, in a 65 nm thin-BOX FD-SOI , 2013, 2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS).

[5]  Huaguo Liang,et al.  Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Xuan Zeng,et al.  A single event upset tolerant latch with parallel nodes , 2019, IEICE Electron. Express.

[7]  Saki Tajima,et al.  Transition Detector-Based Radiation-Hardened Latch for Both Single- and Multiple-Node Upsets , 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

[8]  Jun Xiao,et al.  Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications , 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  Xin Liu,et al.  Multiple Node Upset-Tolerant Latch Design , 2019, IEEE Transactions on Device and Materials Reliability.

[10]  Liyi Xiao,et al.  High robust and cost effective double node upset tolerant latch design for nanoscale CMOS technology , 2019 .

[11]  P. E. Dodd,et al.  Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction , 2013, IEEE Transactions on Nuclear Science.

[12]  Xin Xie,et al.  A novel self-recoverable and triple nodes upset resilience DICE latch , 2018, IEICE Electron. Express.

[13]  Vojin G. Oklobdzija,et al.  Low-Power Soft Error Hardened Latch , 2009, PATMOS.

[14]  Adam R. Duncan,et al.  Multiple-Cell Upsets Induced by Single High-Energy Electrons , 2018, IEEE Transactions on Nuclear Science.

[15]  Yuanqing Li,et al.  Double Node Upsets Hardened Latch Circuits , 2015, J. Electron. Test..

[16]  D. Rossi,et al.  Latch Susceptibility to Transient Faults and New Hardening Approach , 2007, IEEE Transactions on Computers.

[17]  Qiang Zhao,et al.  Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application , 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Huaguo Liang,et al.  A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology , 2015, IEICE Trans. Electron..

[19]  Huaguo Liang,et al.  A High Performance SEU Tolerant Latch , 2015, J. Electron. Test..

[20]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[21]  Fei Yu,et al.  Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits , 2019, J. Electron. Test..

[22]  J. Furuta,et al.  A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop, DICE ACFF, in a 65 nm Thin-BOX FD-SOI , 2014, IEEE Transactions on Nuclear Science.

[23]  Kazutoshi Kobayashi,et al.  Process Dependence of Soft Errors Induced by Alpha Particles, Heavy Ions, and High Energy Neutrons on Flip Flops in FDSOI , 2019, IEEE Journal of the Electron Devices Society.

[24]  Kohei Miyase,et al.  Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments , 2020, IEEE Transactions on Aerospace and Electronic Systems.

[25]  Spyros Tragoudas,et al.  Radiation Hardened Latch Designs for Double and Triple Node Upsets , 2017, IEEE Transactions on Emerging Topics in Computing.

[26]  L. Chen,et al.  A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience , 2017, IEEE Transactions on Nuclear Science.

[27]  Mahdi Fazeli,et al.  Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation , 2013, Microelectron. Reliab..

[28]  Xiaoqing Wen,et al.  Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS , 2018, IEEE Transactions on Emerging Topics in Computing.