Asynchronous Network-on-Chip Communication Architecture Performance Analysis

Network-on-Chip (NoC) designs attempt to solve the performance bottleneck of traditional shared bus designs. Current NoC solutions have drawbacks in area requirements or power consumption. A new architecture is presented to address these problems. Three models of the architecture are implemented in SystemC: a Globally Asynchronous Locally Synchronous (GALS) NoC model, a synchronous NoC model and a shared bus model. The performance of these three models are compared using Poisson distributed traffic with data-rates up to 4 Gbyte/s. Results show a strong case in favor of NoC design over the standard shared bus in large or high-bandwidth systems. For NoC systems, the performance break-even size (number of nodes) compared to a shared bus can be as low as 5 masters, while at a size of 15 nodes the NoC is already about 300% faster than the shared bus. The GALS NoC shows a 24-27% improvement in the delay time compared to the synchronous NoC. The additional design effort and the high bit-error sensitivity in the GALS case need to be addressed before the GALS NoC can be considered as candidate for future on-chip communication. Keywords— Asynchronous Logic Circuit Testing, Network-on-Chip, Performance Analysis, SystemC Model