Low-power CMOS circuits - technology, logic design and CAD tools

TECHNOLOGIES AND DEVICES History of Low-Power Electronics (Christian Piguet, CSEM&LAP-EPFL, Switzerland) Evolution of Deep Submicron Bulk and SOI Technologies (Marc Belleville, Olivier Faynot, CEA-LETI, Grenoble, France) Leakage in CMOS Nanometric Technologies (Antoni Ferre, Joan Figueras, UPC, Barcelona, Spain) Microelectronics, Nanoelectronics and the Future of Electronics" (Jing Wang, Mark Lundstrom, Purdue University, West Lafayette) Advanced Research in On-Chip Optical Interconnects (Ian O'Connor, Frederic Gaffiot, Ecole Centrale de Lyon, Lyon, France) LOW-POWER CIRCUITS Modeling for Designing in Deep Submicron Technologies (Daniel Auvergne, Philippe Maurine, Nadine Azemard, LIRMM, Montpellier, France) Logic Circuits and Standard Cells (Christian Piguet, CSEM&LAP-EPFL, Switzerland) Low-Power Very Fast Dynamic Logic Circuits (Jiren Yuan, Lund University, Sweden) Low-Power Arithmetic Operators (Arnaud Tisserand, INRIA, Lyon, France) Circuit Techniques for Dynamic Power Reduction (Dimitrios Soudris, Democritus University of Thrace, Greece) VHDL for Low-Power (Amara Amara, ISEP, Paris, France and Philippe Royannez, Texas Instruments, France) Clocking Multi-GHz Systems (Vojin G. Oklobdzija, Davis University, CA) Circuit Techniques for Leakage Reduction (Amit Agarwal, Chris H. Kim, Kaushik Roy, Purdue University) Low-Power and Low-Voltage Communication for SoCs (Christer Svensson, Linkoping University, Sweden) Adiabatic and Clock-Powered Circuits (Lars Svensson, Chalmers University, Sweden) Weak Inversion for Ultimate Low-Power Logic (Eric A. Vittoz, CSEM, Switzerland) Robustness of Digital Circuits at Lower Voltages (Harry Veendrick, Philips, Netherlands) CAD TOOLS FOR LOW-POWER High Level Power Estimation and Analysis (Wolfgang Nebel, Oldenburg University, Germany, Domenik Helms, OFFIS, Germany) Power Macro-Models for High-Level Power Estimation (Enrico Macii, Politecnico di Torino, Italy, Massimo Poncino, Universita di Verona, Italy) Synopsys Low-Power Design Flow (Renu Mehra, Barry Pangrle, Synopsys Inc.) Magma Low Power Flow (Ed Huijbregts, Lars Kruse, Eric Seelen, Magma Design Automation Inc.) Sequence Design Flow for Low-Power Design (Jerry Frenkil, Sequence Design)

[1]  David Blaauw,et al.  Analysis and minimization techniques for total leakage considering gate oxide leakage , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[2]  C. Liu,et al.  Circuit requirement and integration challenges of thin gate dielectrics for ultra small MOSFETs , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[3]  J. Wortman,et al.  A comparative study of gate direct tunneling and drain leakage currents in n-MOSFET's with sub-2 nm gate oxides , 2000 .

[4]  Vassilis Paliouras,et al.  Low-power properties of the logarithmic number system , 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.

[5]  H.-S.P. Wong,et al.  Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[6]  Mohamed I. Elmasry,et al.  Power dissipation analysis and optimization of deep submicron CMOS digital circuits , 1996, IEEE J. Solid State Circuits.

[7]  Gabriella Ghidini,et al.  Gate current in ultrathin MOS capacitors: a new model of tunnel current , 2001 .

[8]  Michael J. Schulte,et al.  Reduced power dissipation through truncated multiplication , 1999, Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design.

[9]  Keith A. Bowman,et al.  A minimum total power methodology for projecting limits on CMOS GSI , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[10]  M. Shur,et al.  Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFETs , 1993 .

[11]  D. Frank,et al.  Discrete random dopant distribution effects in nanometer-scale MOSFETs , 1998 .

[12]  Carver Mead.  Scaling of MOS technology to submicrometer feature sizes , 1994, J. VLSI Signal Process..

[13]  M. Bohr.  Nanotechnology goals and challenges for electronic applications , 2002 .

[14]  Magdy Bayoumi,et al.  A novel high-performance CMOS 1-bit full-adder cell , 2000 .

[15]  Masayuki Fujita,et al.  Ultrasmall and ultralow threshold GaInAsP-InP microdisk injection lasers: design, fabrication, lasing characteristics, and spontaneous emission factor , 1999 .

[16]  John Whittaker,et al.  Rules of Thumb , 1996 .

[17]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.

[18]  H. Wong,et al.  CMOS scaling into the nanometer regime , 1997, Proc. IEEE.

[19]  Karl Hess,et al.  Tunneling through ultrathin SiO2 gate oxides from microscopic models , 2001 .

[20]  S. Sze.  High-speed semiconductor devices , 1990 .

[21]  Bin Yu,et al.  Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET's , 1997 .

[22]  Stephen H. Unger,et al.  Clocking Schemes for High-Speed Digital Systems , 1986, IEEE Transactions on Computers.

[23]  Uming Ko,et al.  Low-power design techniques for high-performance CMOS adders , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[24]  Kazuo Horie,et al.  A complete substrate current model including band-to-band tunneling current for circuit simulation , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  J. Meindl,et al.  A circuit-level perspective of the optimum gate oxide thickness , 2001 .

[26]  Mark S. Lundstrom,et al.  On the performance limits for Si MOSFETs: a theoretical study , 2000 .

[27]  M.A. Horowitz,et al.  Skew-tolerant domino circuits , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[28]  Randall D. Isaac.  The future of CMOS technology , 2000, IBM J. Res. Dev..

[29]  Paolo Antognetti,et al.  Semiconductor Device Modeling with Spice , 1988 .

[30]  Shih-Wei Sun,et al.  A closed-form back-gate-bias related inverse narrow-channel effect model for deep-submicron VLSI CMOS devices using shallow trench isolation , 2000 .

[31]  Alain Guyot,et al.  Modeling power consumption in arithmetic operators , 1997 .

[32]  H. Nayfeh,et al.  Strained silicon MOSFET technology , 2002, Digest. International Electron Devices Meeting,.

[33]  Scott Hauck,et al.  Asynchronous design methodologies: an overview , 1995, Proc. IEEE.

[34]  F. Weber,et al.  Flow-through latch and edge-triggered flip-flop hybrid elements , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[35]  Mohamed I. Elmasry,et al.  Circuit techniques for CMOS low-power high-performance multipliers , 1996 .

[36]  Jean-Michel Muller,et al.  Elementary Functions: Algorithms and Implementation , 1997 .

[37]  James Tschanz,et al.  Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors , 2001, ISLPED '01.

[38]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[39]  K. Gopalakrishnan,et al.  I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q , 2002, Digest. International Electron Devices Meeting,.

[40]  Douglas Yu,et al.  Characterization and modeling of edge direct tunneling (EDT) leakage in ultrathin gate oxide MOSFETs , 2001 .

[41]  M. Notomi,et al.  Structural tuning of guiding modes of line-defect waveguides of silicon-on-insulator photonic crystal slabs , 2002 .

[42]  S. Mudanai,et al.  Modeling of direct tunneling current through gate dielectric stacks , 2000 .

[43]  Perry A. Zirkel.  Don't Touch! , 2000 .

[44]  Ching-Yuan Wu,et al.  A new quasi-2-D model for hot-carrier band-to-band tunneling current , 1999 .

[45]  Bogdan Majkusiak,et al.  Semiconductor thickness and back-gate voltage effects on the gate tunnel current in the MOS/SOI system with an ultrathin oxide , 2000 .

[46]  Michael J. Flynn,et al.  Division Algorithms and Implementations , 1997, IEEE Trans. Computers.

[47]  David J. Frank,et al.  Nanoscale CMOS , 1999, Proc. IEEE.

[48]  Eby G. Friedman,et al.  Clock distribution networks in synchronous digital integrated circuits , 2001, Proc. IEEE.

[49]  Anantha Chandrakasan,et al.  Scaling of stack effect and its application for leakage reduction , 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

[50]  A. O. Adan,et al.  OFF-State leakage current mechanisms in bulkSi and SOI MOSFETs and their impact on CMOS ULSIs standby current , 2001 .

[51]  Vwani P. Roychowdhury,et al.  RF/wireless interconnect for inter- and intra-chip communications , 2001, Proc. IEEE.

[52]  Kaushik Roy,et al.  Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[53]  Kaustav Banerjee,et al.  3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.

[54]  Johnny Öberg,et al.  Lowering power consumption in clock by using globally asynchronous locally synchronous design style , 1999, DAC '99.

[55]  C. Hu,et al.  Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling , 2001 .

[56]  K. Takeuchi,et al.  A study of the threshold voltage variation for ultra-small bulk and SOI CMOS , 2001 .

[57]  Joan Figueras,et al.  Leakage power bounds in CMOS digital technologies , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[58]  Toshihiko Baba,et al.  Photonic crystals and microdisk cavities based on GaInAsP-InP system , 1997 .

[59]  P.C. Maxwell,et al.  A simulation-based method for estimating defect-free I/sub DDQ/ , 1997, Digest of Papers IEEE International Workshop on IDDQ Testing.

[60]  Tomás Lang,et al.  Low-Power Divider , 1999, IEEE Trans. Computers.

[61]  Chenming Hu,et al.  MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations , 2003 .

[62]  R. Ravi,et al.  Optimal Circuits for Parallel Multipliers , 1998, IEEE Trans. Computers.

[63]  S. M. Sze,et al.  Modern semiconductor device physics , 1997 .

[64]  J. Liaw,et al.  Leakage scaling in deep submicron CMOS for SoC , 2002 .

[65]  Chuan Yi Tang,et al.  A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..

[66]  Yuan Taur,et al.  Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.

[67]  Leonard W. Cotten.  Circuit implementation of high-speed pipeline systems , 1965, AFIPS '65 (Fall, part I).

[68]  Jeong-Mo Hwang,et al.  Accurate extraction of reverse leakage current components of shallow silicided p/sup +/-n junction for quarter- and sub-quarter-micron MOSFET's , 1998 .

[69]  Reto Zimmermann,et al.  Binary adder architectures for cell-based VLSI and their synthesis , 1997 .

[70]  Ashutosh Das,et al.  A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors , 1999 .

[71]  Massimo Alioto,et al.  Analysis and comparison on full adder block in submicron technology , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[72]  T. Ono,et al.  Limit of gate oxide thickness scaling in MOSFETs due to apparent threshold voltage fluctuation induced by tunnel leakage current , 2001 .

[73]  Doris Schmitt-Landsiedel,et al.  The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits , 1996, ISLPED '96.

[74]  C. Hu,et al.  BSIM4 gate leakage model including source-drain partition , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[75]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[76]  Hiroshi Iwai,et al.  CMOS technology-year 2010 and beyond , 1999, IEEE J. Solid State Circuits.

[77]  Sarah-Jane Dodd,et al.  Addition and Subtraction , 2003 .

[78]  Stefan Kubicek,et al.  Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime , 2000 .

[79]  J. R. Brews,et al.  Comparison of deep-submicrometer conventional and retrograde n-MOSFETs , 2000 .

[80]  W. Liu,et al.  Wave-pipelining: a tutorial and research survey , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[81]  S. Laux,et al.  Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys , 1996 .

[82]  Michael J. Flynn,et al.  Advanced Computer Arithmetic Design , 2001 .

[83]  Mark Storey,et al.  Microprocessor IDDQ Testing: A Case Study , 1995, IEEE Des. Test Comput..

[84]  D. Burnett,et al.  Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits , 1994, Proceedings of 1994 VLSI Technology Symposium.

[85]  Chin-Shan Hou,et al.  Back-gate bias enhanced band-to-band tunneling leakage in scaled MOSFET's , 1998 .

[86]  Chenming Hu,et al.  Comparison of GIDL in p/sup +/-poly PMOS and n/sup +/-poly PMOS devices , 1996, IEEE Electron Device Letters.

[87]  Yoshio Murakami,et al.  Separation and analysis of diffusion and generation components of pn junction leakage current in various silicon wafers , 1994 .