*-Predictable MPSoC execution of real-time control applications using invasive computing: *Predictable MPSoC execution of real-time control applications using invasive computing
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[1] Mario Porrmann,et al. Self-optimization of MPSoCs Targeting Resource Efficiency and Fault Tolerance , 2009, 2009 NASA/ESA Conference on Adaptive Hardware and Systems.
[2] Michael Glaß,et al. A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs , 2018, ACM Trans. Embed. Comput. Syst..
[3] Leslie Lamport,et al. The parallel execution of DO loops , 1974, CACM.
[4] Paolo Meloni,et al. System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach , 2012, 2012 15th Euromicro Conference on Digital System Design.
[5] Jürgen Teich,et al. Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays , 2015, SCOPES.
[6] Jürgen Teich,et al. A highly parameterizable parallel processor array architecture , 2006, 2006 IEEE International Conference on Field Programmable Technology.
[7] Radu Marculescu,et al. FARM: Fault-aware resource management in NoC-based multiprocessor platforms , 2011, 2011 Design, Automation & Test in Europe.
[8] Jürgen Teich,et al. Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures , 2014, 2014 17th Euromicro Conference on Digital System Design.
[9] Stephen A. Edwards,et al. Predictable programming on a precision timed architecture , 2008, CASES '08.
[10] Jürgen Teich,et al. A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays , 2015, 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).
[11] Rami G. Melhem,et al. Loop Transformations for Fault Detection in Regular Loops on Massively Parallel Systems , 1996, IEEE Trans. Parallel Distributed Syst..
[12] Jürgen Teich,et al. On-demand fault-tolerant loop processing on massively parallel processor arrays , 2015, 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP).
[13] Jürgen Teich,et al. Techniques for on-demand structural redundancy for massively parallel processor arrays , 2015, J. Syst. Archit..
[14] D. Kissler,et al. Hardware Cost Analysis for Weakly Programmable Processor Arrays , 2006, 2006 International Symposium on System-on-Chip.
[15] Jürgen Teich,et al. A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template , 2006, ReCoSoC.
[16] Greg Stitt,et al. Elastic computing: a framework for transparent, portable, and adaptive multi-core heterogeneous computing , 2010, LCTES '10.
[17] Vivek Sarkar,et al. X10: an object-oriented approach to non-uniform cluster computing , 2005, OOPSLA '05.
[18] Jürgen Teich,et al. Symbolic inner loop parallelisation for massively parallel processor arrays , 2014, 2014 Twelfth ACM/IEEE Conference on Formal Methods and Models for Codesign (MEMOCODE).
[19] Jürgen Teich,et al. Decentralized dynamic resource management support for massively parallel processor arrays , 2011, ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors.
[20] Dionisios N. Pnevmatikatos,et al. The DeSyRe Runtime Support for Fault-Tolerant Embedded MPSoCs , 2014, 2014 IEEE International Symposium on Parallel and Distributed Processing with Applications.
[21] Jürgen Teich,et al. System integration of tightly-coupled processor arrays using reconfigurable buffer structures , 2013, CF '13.
[22] Jürgen Teich,et al. Resource-aware programming and simulation of MPSoC architectures through extension of X10 , 2011, SCOPES.
[23] Jürgen Teich,et al. Symmetry-Eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[24] Cristiana Bolchini. A software methodology for detecting hardware faults in VLIW data paths , 2003, IEEE Trans. Reliab..
[25] Lothar Thiele,et al. Design for Timing Predictability , 2004, Real-Time Systems.
[26] Jürgen Teich,et al. The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure , 2014, ARCS Workshops.
[27] Michael Glaß,et al. Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution Using Invasive Computing , 2016, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC).
[28] Jürgen Teich,et al. Invasive Computing: An Overview , 2011, Multiprocessor System-on-Chip.
[29] Jürgen Teich,et al. Symbolic parallelization of loop programs for massively parallel processor arrays , 2013, 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors.
[30] Jürgen Teich,et al. Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study , 2018, 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP).
[31] Masanori Hashimoto,et al. Coarse-grained dynamically reconfigurable architecture with flexible reliability , 2009, 2009 International Conference on Field Programmable Logic and Applications.
[32] Jürgen Teich,et al. Massively Parallel Processor Architectures for Resource-aware Computing , 2014, ArXiv.
[33] Jürgen Teich,et al. Loop program mapping and compact code generation for programmable hardware accelerators , 2013, 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors.
[34] Frank Hannig,et al. Invasive Tightly-Coupled Processor Arrays , 2014, ACM Trans. Embed. Comput. Syst..
[35] Henry Hoffmann,et al. Application heartbeats: a generic interface for specifying program performance and goals in autonomous computing environments , 2010, ICAC '10.
[36] Jürgen Becker,et al. A Scalable NoC Router Design Providing QoS Support Using Weighted Round Robin Scheduling , 2012, 2012 IEEE 10th International Symposium on Parallel and Distributed Processing with Applications.
[37] Jürgen Teich,et al. Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures , 2009, J. Low Power Electron..
[38] Jürgen Teich,et al. Invasive computing for predictable stream processing: a simulation-based case study , 2015, 2015 13th IEEE Symposium on Embedded Systems For Real-time Multimedia (ESTIMedia).
[39] Jürgen Teich,et al. Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays , 2015, 2015 ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE).
[40] Jürgen Teich,et al. Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms , 2014, 2014 48th Asilomar Conference on Signals, Systems and Computers.
[41] Jürgen Teich,et al. Symbolic Mapping of Loop Programs onto Processor Arrays , 2014, J. Signal Process. Syst..