A first-order analysis of the impact of technology scaling on the performance parameters of linear CMOS analog circuits is presented. Scaling of single gain stage and two-stage operational amplifier small-signal performance parameters is examined under the constant field (CE), quasi-constant voltage (QCV), and constant voltage (CV) scaling rules; in addition to classical full scaling, other practical analog scaling options such as constant device size (W and L), constant total dc bias current, and constant power dissipation are also considered. A computeraided design tool that accurately and rapidly resizes linear analog standard cells in short-channel CMOS processes using SPICEquality device models and constrained optimization techniques is described. The CAD tool is applied to redesign a two-stage opamp in 5 pm, 3 pm and 2 pm p-well CMOS technologies for both minimum power dissipation and minimum die area objectives using modified constant voltage (Vdd = 5 v) scaling rules. About 10 seconds of computer time on a DEC 3100 are required per optimized redesign.
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