Application-specific CAD of VLSI second-order sections

An application-specific, very-high-level CAD (computer-aided design) tool is presented for producing very-high-throughput IIT (infinite-impulse response) filters. The architecture is a cascade of blocked, pipelined, second-order sections. It is necessary only to specify the word size w, the block size B, and each second-order section's coefficients. Using this information, the CAD tool will generate Celtech intermediate-form files for a filter system that at 10 MHz can process 5B/w million samples/s: the benefits of applying both bit-level array architecture and application-specific CAD to the problem of IIR filtering are illustrated. The resulting CAD system reduces the costs of very-high-throughput IIR filters with respect to design, fabrication, and operation. >

[1]  Keshab K. Parhi,et al.  Look-ahead computation: Improving iteration bound in linear recursions , 1987, ICASSP '87. IEEE International Conference on Acoustics, Speech, and Signal Processing.

[2]  H. T. Kung Why systolic architectures? , 1982, Computer.

[3]  G. Goossens,et al.  Custom design of a VLSI PCM-FDM transmultiplexer from system specifications to circuit layout using a computer-aided design system , 1986 .

[4]  Albert Benveniste,et al.  Signal-A data flow-oriented language for signal processing , 1986, IEEE Trans. Acoust. Speech Signal Process..

[5]  S. Mitra,et al.  Block implementation of recursive digital filters--New structures and properties , 1978 .

[6]  Keshab K. Parhi,et al.  BLOCK DIGITAL FILTERING VIA INCREMENTAL BLOCK-STATE STRUCTURE. , 1987 .

[7]  Chrysostomos L. Nikias,et al.  Fast block data processing via a new IIR digital filter structure , 1984 .

[8]  T. Meng,et al.  Arbitrarily high sampling rate adaptive filters , 1987, IEEE Trans. Acoust. Speech Signal Process..

[9]  H. Voelcker,et al.  Digital filtering via block recursion , 1970 .

[10]  John G. McWhirter,et al.  Completely iterative, pipelined multiplier array suitable for VLSI , 1982 .

[11]  James B. Angell,et al.  Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic , 1973, IEEE Transactions on Computers.

[12]  Robert W. Brodersen,et al.  Computer Generation of Digital Filter Banks , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  C. Burrus Block implementation of digital filters , 1971 .

[14]  J. Vuillemin,et al.  Recursive implementation of optimal time VLSi integer multipliers , 1984 .

[15]  Edward A. Lee,et al.  Fast recursive filtering with multiple slow processing elements , 1985 .

[16]  P. R. Cappello,et al.  An Air Filter Tissue , 1985, Nineteeth Asilomar Conference on Circuits, Systems and Computers, 1985..

[17]  Richard F. Lyon,et al.  Two's Complement Pipeline Multipliers , 1976, IEEE Trans. Commun..

[18]  Keshab K. Parhi,et al.  AREA-EFFICIENT HIGH SPEED VLSI ADAPTIVE FILTER ARCHITECTURES. , 1987 .

[19]  Keshab K. Parhi,et al.  Concurrent cellular VLSI adaptive filter architectures , 1987 .

[20]  Walter S. Scott,et al.  1986 VLSI Tools: Still More Works by the Original Artists , 1985 .

[21]  Peter R. Cappello,et al.  A note on 'free accumulation' in VLSI filter architectures , 1985 .

[22]  D. V. Bhaskar Rao,et al.  Wavefront Array Processor: Language, Architecture, and Applications , 1982, IEEE Transactions on Computers.

[23]  Peter B. Denyer,et al.  VLSI Signal Processing: A Bit-Serial Approach , 1985 .

[24]  Keshab K. Parhi,et al.  BIT PARALLEL BIT LEVEL RECURSIVE FILTER ARCHITECTURE. , 1986 .

[25]  P.R. Cappello,et al.  Computer-aided design of VLSI FIR filters , 1987, Proceedings of the IEEE.