A low power VLSI architecture of SOVA-based turbo-code decoder using scarce state transition scheme

In this paper, we propose a low power VLSI architecture of Soft-Output-Viterbi-Algorithm (SOVA) based turbo-code decoder using a scarce state transition scheme (SST). A register exchange survival memory unit (RE-SMU) and systolic block are used in the implementation of SOVA for high throughput and low latency. SST is used to reduce the power consumption. Simulation results show that the power consumption of RE-SMU and the systolic block is reduced significantly. The power consumption of the add-compare-select (ACS) block is also reduced by as much as 20% after 4 iterations of turbo-code decoding.

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