Embedded high-speed BCH decoder for new-generation NOR flash memories

A high-speed double-error-correcting (DEC) BCH decoder for new-generation NOR flash memory is presented to improve reliability. To speed up the decoding process, a multiplication-free linear transform is developed to eliminate iterations and divisions in Galois fields. Furthermore, a reverse data-flow analysis (RDFA) and smoothest descent approach are proposed to reduce latency in the bit-parallel Chien search. Based on peripheral 180nm CMOS process, the whole BCH decoder is designed and the latency is significantly reduced to less than 5ns.

[1]  Eiji Fujiwara,et al.  Error-control coding for computer systems , 1989 .

[2]  Guido Torelli,et al.  On-chip error correcting techniques for new-generation flash memories , 2003, Proc. IEEE.

[3]  D. Strukov,et al.  The area and latency tradeoffs of binary bit-parallel BCH decoders for prospective nanoelectronic memories , 2006, 2006 Fortieth Asilomar Conference on Signals, Systems and Computers.

[4]  Luca Crippa,et al.  A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[5]  Patrick Schaumont,et al.  A new algorithm for elimination of common subexpressions , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Shyue-Win Wei,et al.  A high-speed real-time binary BCH decoder , 1993, IEEE Trans. Circuits Syst. Video Technol..

[7]  Robert S. Schriebman.  Error Correcting Code , 2006 .

[8]  Miodrag Potkonjak,et al.  Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..