Thermo-compression bonding assembly process and reliability studies of Cu pillar bump on Cu/Low-K Chip
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F. X. Che | Jong-Kai Lin | K. Y. Au | Bjoern Boehme | Frank Kuechenmeister | Jie Li Aw | F. Che | B. Boehme | Jong-Kai Lin | J. Aw | F. Kuechenmeister
[1] Yasumitsu Orii,et al. Ultrafine-pitch C2 flip chip interconnections with solder-capped Cu pillar bumps , 2009, 2009 59th Electronic Components and Technology Conference.
[2] M. Gaynes,et al. Wafer level underfill for area array Cu pillar flip chip packaging of ultra low-k chips on organic substrates , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.
[3] Nokibul Islam,et al. Optimization of Compression Bonding processing temperature for fine pitch Cu-column flip chip devices , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).
[4] Virendra Jadhav,et al. Flip chip assembly challenges using high density, thin core carriers , 2005, Proceedings Electronic Components and Technology, 2005. ECTC '05..
[5] Mike Ma,et al. Development of thermal compression bonding with Non Conductive Paste for 3DIC fine pitch copper pillar bump interconnections , 2011, 2011 IEEE 13th Electronics Packaging Technology Conference.
[6] Michael Gaynes,et al. High performance wafer level underfill material with high filler loading , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).
[7] Vempati Srinivasa Rao,et al. Development of bonding process for high density fine pitch micro bump interconnections with wafer level underfill for 3D applications , 2013, 2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013).
[8] Nokibul Islam,et al. Study of FCMBGA with low CTE core substrate , 2009, 2009 59th Electronic Components and Technology Conference.
[9] Curtis Zwenger,et al. Study of interconnection process for fine pitch flip chip , 2009, 2009 59th Electronic Components and Technology Conference.