5GHz 4-Phase Integer-N All-Digital PLL의 설계

This paper introduces the implementation of Integer-N All-Digital PLL(Phase-Locked Loop), which synthesizes 5GHz 4-phase(0˚, 90˚, 180˚, 270˚) clocks. This PLL is implemented in TSMC 65nm process. The estimated phase noise and RMS jitter of this PLL are - 116dBc/Hz @20MHz and 1.89ps.