A joined architecture/compiler design environment for ASIPs

In this paper, we introduce a methodology for rapid prototyping of application-speci c instruction set processors (ASIPs) including the automatic generation of bit-true and cycle-accurate instruction-set simulators and corresponding compiler (re)targets. The methodology is based on ASMs (abstract state machines) as the underlying formal model for describing a processor's behavior. We explain the major advantages of using ASMs and outline the main tool ow from graphical entry of a processor's major RTL building blocks and simulator generation as well as the current status of our project.

[1]  Markus Freericks,et al.  Describing instruction set processors using nML , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[2]  Heinrich Meyr,et al.  LISA—machine description language for cycle-accurate models of programmable DSP architectures , 1999, DAC '99.

[3]  Steve Furber,et al.  ARM System Architecture , 1996 .

[4]  Matthias Anlauff,et al.  XASM - An Extensible, Component-Based ASM Language , 2000, Abstract State Machines.

[5]  Andreas Fauth.  Beyond tool-specific machine descriptions , 1994, Code Generation for Embedded Processors.

[6]  Pierre G. Paulin,et al.  Flexware: A flexible firmware development environment for embedded systems , 1994, Code Generation for Embedded Processors.

[7]  Heinrich Meyr,et al.  Retargeting of compiled simulators for digital signal processors using a machine description language , 2000, DATE '00.

[8]  Yuri Gurevich,et al.  Evolving algebras 1993: Lipari guide , 1995, Specification and validation methods.

[9]  G. Goossens,et al.  PROGRAMMABLE CHIPS IN CONSUMER ELECTRONICS AND TELECOMMUNICATIONS , 1996 .

[10]  Jürgen Teich,et al.  Description and Simulation of Microprocessor Instruction Sets Using ASMs , 2000, Abstract State Machines.

[11]  Alfonso Pierantonio,et al.  Formal aspects of and development environments for Montages , 1997 .

[12]  Gert Goossens,et al.  Chess: retargetable code generation for embedded DSP processors , 1994, Code Generation for Embedded Processors.

[13]  Rainer Leupers,et al.  Retargetable Code Generation for Digital Signal Processors , 1997, Springer US.

[14]  Heinrich Theodor Vierhaus,et al.  Local microcode generation in system design , 1994, Code Generation for Embedded Processors.