Differential Power Analysis Attacks to Precharged Buses: A General Analysis for Symmetric-Key Cryptographic Algorithms

In this paper, a general model of multibit Differential Power Analysis (DPA) attacks to precharged buses is discussed, with emphasis on symmetric-key cryptographic algorithms. Analysis provides a deeper insight into the dependence of the DPA effectiveness (i.e., the vulnerability of cryptographic chips) on the parameters that define the attack, the algorithm, and the processor architecture in which the latter is implemented. To this aim, the main parameters that are of interest in practical DPA attacks are analytically derived under appropriate approximations, and a novel figure of merit to measure the DPA effectiveness of multibit attacks is proposed. This figure of merit allows for identifying conditions that maximize the effectiveness of DPA attacks, i.e., conditions under which a cryptographic chip should be tested to assess its robustness. Several interesting properties of DPA attacks are derived, and suggestions to design algorithms and circuits with higher robustness against DPA are given. The proposed model is validated in the case of DES and AES algorithms with both simulations on an MIPS32 architecture and measurements on an FPGA-based implementation of AES. The model accuracy is shown to be adequate, as the resulting error is always lower than 10 percent and typically of a few percentage points.

[1]  Ingrid Verbauwhede,et al.  Charge recycling sense amplifier based logic: securing low power security ICs against DPA [differential power analysis] , 2004, Proceedings of the 30th European Solid-State Circuits Conference.

[2]  Kevin Barraclough,et al.  I and i , 2001, BMJ : British Medical Journal.

[3]  Paul C. Kocher,et al.  Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems , 1996, CRYPTO.

[4]  Jean-Jacques Quisquater,et al.  A Practical Implementation of the Timing Attack , 1998, CARDIS.

[5]  Aarnout Brombacher,et al.  Probability... , 2009, Qual. Reliab. Eng. Int..

[6]  Thomas S. Messerges,et al.  Investigations of Power Analysis Attacks on Smartcards , 1999, Smartcard.

[7]  Stefan Mangard,et al.  Power analysis attacks - revealing the secrets of smart cards , 2007 .

[8]  Robert H. Sloan,et al.  Examining Smart-Card Security under the Threat of Power Analysis Attacks , 2002, IEEE Trans. Computers.

[9]  W. V. Eck.  Electromagnetic Radiation from Video Display Units: An Eavesdropping Risk? , 1996 .

[10]  Claude E. Shannon,et al.  Communication theory of secrecy systems , 1949, Bell Syst. Tech. J..

[11]  Yusuf Leblebici,et al.  Low-power current mode logic for improved DPA-resistance in embedded systems , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[12]  S. Yang,et al.  AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks , 2006, IEEE Journal of Solid-State Circuits.

[13]  I. Verbauwhede,et al.  A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards , 2002, Proceedings of the 28th European Solid-State Circuits Conference.

[14]  D. Owen.  Handbook of Mathematical Functions with Formulas , 1965 .

[15]  Massimo Alioto,et al.  Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm , 2006, PATMOS.

[16]  Alfred Menezes,et al.  Handbook of Applied Cryptography , 2018 .

[17]  Massimo Alioto,et al.  A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Alessandro Trifiletti,et al.  Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[19]  Narayanan Vijaykrishnan,et al.  Power attack resistant cryptosystem design: a dynamic voltage and frequency switching approach , 2005, Design, Automation and Test in Europe.

[20]  M. Anwar Hasan.  Power Analysis Attacks and Algorithmic Approaches to their Countermeasures for Koblitz Curve Cryptosystems , 2000, CHES.

[21]  Mark G. Karpovsky,et al.  Delay insensitive encoding and power analysis: a balancing act [cryptographic hardware protection] , 2005, 11th IEEE International Symposium on Asynchronous Circuits and Systems.

[22]  Massimo Alioto,et al.  Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis , 2006, PATMOS.

[23]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[24]  Christophe Clavier,et al.  Differential Power Analysis in the Presence of Hardware Countermeasures , 2000, CHES.

[25]  R. Stephenson.  A and V , 1962, The British journal of ophthalmology.

[26]  Stefan Mangard,et al.  Hardware Countermeasures against DPA ? A Statistical Analysis of Their Effectiveness , 2004, CT-RSA.

[27]  Louis Goubin,et al.  DES and Differential Power Analysis (The "Duplication" Method) , 1999, CHES.

[28]  Athanasios Papoulis,et al.  Probability, Random Variables and Stochastic Processes , 1965 .

[29]  William Stallings,et al.  Cryptography and Network Security: Principles and Practice , 1998 .

[30]  Lionel Torres,et al.  Hardware engines for bus encryption: a survey of existing techniques , 2005, Design, Automation and Test in Europe.

[31]  Tao Zhang,et al.  HIDE: an infrastructure for efficiently protecting information leakage on the address bus , 2004, ASPLOS XI.

[32]  Alessandro Trifiletti,et al.  A countermeasure against differential power analysis based on random delay insertion , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[33]  Milton Abramowitz,et al.  Handbook of Mathematical Functions with Formulas, Graphs, and Mathematical Tables , 1964 .

[34]  Travis N. Blalock,et al.  An on-chip signal suppression countermeasure to power analysis attacks , 2004, IEEE Transactions on Dependable and Secure Computing.

[35]  Ingrid Verbauwhede,et al.  A VLSI design flow for secure side-channel attack resistant ICs , 2005, Design, Automation and Test in Europe.

[36]  Elisabeth Oswald,et al.  Differential Power Analysis of an AES Implementation , 2004 .

[37]  Eli Biham,et al.  Differential Fault Analysis of Secret Key Cryptosystems , 1997, CRYPTO.

[38]  Marc Renaudin,et al.  DPA on quasi delay insensitive asynchronous circuits: formalization and improvement , 2005, Design, Automation and Test in Europe.

[39]  Erik P. de Vink,et al.  Virtual Analysis and Reduction of Side-Channel Vulnerabilities of Smartcards , 2004, Formal Aspects in Security and Trust.

[40]  Aaas News,et al.  Book Reviews , 1893, Buffalo Medical and Surgical Journal.

[41]  Tim Collins,et al.  Secure contactless smartcard ASIC with DPA protection , 2001 .

[42]  Alessandro Trifiletti,et al.  A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors , 2004, PATMOS.

[43]  Patrick Schaumont,et al.  A side-channel leakage free coprocessor IC in 0.18/spl mu/m CMOS for embedded AES-based cryptographic and biometric processing , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[44]  Rung-Bin Lin,et al.  Theoretical analysis of bus-invert coding , 2002, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[45]  Richard J. Lipton,et al.  On the Importance of Checking Cryptographic Protocols for Faults (Extended Abstract) , 1997, EUROCRYPT.

[46]  James Irwin,et al.  Using media processors for low-memory AES implementation , 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.

[47]  Paul C. Kocher,et al.  Differential Power Analysis , 1999, CRYPTO.

[48]  Bruno O. Shubert,et al.  Random variables and stochastic processes , 1979 .

[49]  Adi Shamir,et al.  Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies , 2000, CHES.

[50]  Wolfgang Rankl,et al.  Smart Card Handbook , 1997 .