A fully integrated 24-GHz phased-array transmitter in CMOS

This paper presents the first fully integrated 24-GHz phased-array transmitter designed using 0.18-/spl mu/m CMOS transistors. The four-element array includes four on-chip CMOS power amplifiers, with outputs matched to 50 /spl Omega/, that are each capable of generating up to 14.5 dBm of output power at 24 GHz. The heterodyne transmitter has a two-step quadrature up-conversion architecture with local oscillator (LO) frequencies of 4.8 and 19.2 GHz, which are generated by an on-chip frequency synthesizer. Four-bit LO path phase shifting is implemented in each element at 19.2 GHz, and the transmitter achieves a peak-to-null ratio of 23 dB with raw beam-steering resolution of 7/spl deg/ for radiation normal to the array. The transmitter can support data rates of 500 Mb/s on each channel (with BPSK modulation) and occupies 6.8 mm /spl times/ 2.1 mm of die area.

[1]  D.J. Allstot,et al.  A low-loss phase shifter in 180 nm CMOS for multiple-antenna receivers , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[2]  Xiang Guan,et al.  A fully integrated 24-GHz eight-element phased-array receiver in silicon , 2004, IEEE Journal of Solid-State Circuits.

[3]  David B. Rutledge,et al.  The Electronics of Radio , 1999 .

[4]  J. Ryynanen,et al.  A 22 mA 3.7 dB NF direct conversion receiver for 3G WCDMA , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[5]  Behzad Razavi,et al.  A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector , 2003, IEEE J. Solid State Circuits.

[6]  C. E. SHANNON,et al.  A mathematical theory of communication , 1948, MOCO.

[7]  D. Parker,et al.  Microwave industry outlook - defense applications , 2002 .

[8]  Claude E. Shannon,et al.  A Mathematical Theory of Communications , 1948 .

[9]  D. Parker,et al.  Phased arrays - part 1: theory and architectures , 2002 .

[10]  A. Hajimiri,et al.  A 24-GHz, +14.5-dBm fully integrated power amplifier in 0.18-/spl mu/m CMOS , 2005, IEEE Journal of Solid-State Circuits.

[11]  D. Parker,et al.  Phased arrays-part II: implementations, applications, and future trends , 2002 .

[12]  T.S.D. Cheung,et al.  On-chip interconnect for mm-wave applications using an all-copper technology and wavelength reduction , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[13]  R. Bansal,et al.  Antenna theory; analysis and design , 1984, Proceedings of the IEEE.

[14]  David B. Rutledge,et al.  A 24-GHz Patch Array with a Power Amplifier/Low-Noise Amplifier MMIC , 2002 .

[15]  Rumi Chunara,et al.  Phased array systems in silicon , 2004, IEEE Communications Magazine.

[16]  Zhaofeng Zhang,et al.  A 930 MHz CMOS DC-offset-free direct-conversion 4-FSK receiver , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[17]  Donald K. Weaver,et al.  A Third Method of Generation and Detection of Single-Sideband Signals , 1956, Proceedings of the IRE.

[18]  A. Hajimiri,et al.  A 24GHz, +14.5dBm fully-integrated power amplifier in 0.18 /spl mu/m CMOS , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[19]  Ali Hajimiri,et al.  A 24 GHz phased-array transmitter in 0.18 /spl mu/m CMOS , 2005 .

[20]  Geoffrey Ye Li,et al.  Broadband MIMO-OFDM wireless communications , 2004, Proceedings of the IEEE.

[21]  Brian Ellis The Design of CMOS Radio-Frequency Integrated Circuits , 2004 .

[22]  Tanaka Satoshi,et al.  A Loop-Bandwidth Calibration System for Fractional-N Synthesizer and ΔΣ PLL Transmitter , 2005 .

[23]  J. Paramesh,et al.  A 1.4V 5GHz four-antenna Cartesian-combining receiver in 90nm CMOS for beamforming and spatial diversity applications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[24]  Thomas H. Lee,et al.  The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES , 2003 .

[25]  Meng-Chang Lee,et al.  All-digital PLL and GSM/EDGE transmitter in 90nm CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[26]  H. Hashemi,et al.  A 24-GHz SiGe phased-array receiver-LO phase-shifting approach , 2005, IEEE Transactions on Microwave Theory and Techniques.

[27]  M. Kawabe,et al.  A loop-bandwidth calibration system for fractional-N synthesizer and /spl Delta//spl Sigma/-PLL transmitter , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[28]  Robert C. Hansen,et al.  Significant phased array papers , 1973 .

[29]  B. Jagannathan,et al.  A 0.18 /spl mu/m BiCMOS technology featuring 120/100 GHz (f/sub T//f/sub max/) HBT and ASIC-compatible CMOS using copper interconnect , 2001, Proceedings of the 2001 BIPOLAR/BiCMOS Circuits and Technology Meeting (Cat. No.01CH37212).

[30]  M. Chua,et al.  1 GHz programmable analog phase shifter for adaptive antennas , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).