Classifying Functions with Exact Synthesis

Due to recent advances, constraint solvers have become efficient tools for synthesizing optimum Boolean circuits. We take advantage of this by showing how SAT based exact synthesis may be used as a method for finding minimum length Boolean chains. As opposed to other exact synthesis methods, ours may be easily parallelized, which we use to obtain a speedup of approximately 48 times. By combining our method with NPN canonization, we find for the first time the minimum length chains for all 4- and 5-input functions in terms of 3-input Boolean operators. Finally, we propose a hardware acceleration method for NPN canonization. It can be used to speed up NPN canonization in existing algorithms, and we believe it will allow us to find all 6-input NPN classes as well.

[1]  Cody Murray,et al.  On the (Non) NP-Hardness of Computing Circuit Complexity , 2015, Theory Comput..

[2]  Giovanni De Micheli,et al.  Fast hierarchical NPN classification , 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

[3]  Michael A. Harrison,et al.  The Number of Equivalence Classes of Boolean Functions Under Groups Containing Negation , 1963, IEEE Trans. Electron. Comput..

[4]  Robert K. Brayton,et al.  Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT , 2016, SAT.

[5]  Robert K. Brayton,et al.  DAG-aware AIG rewriting: a fresh look at combinational logic synthesis , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[6]  Johan Håstad,et al.  Almost optimal lower bounds for small depth circuits , 1986, STOC '86.

[7]  Eric Allender,et al.  Uniform constant-depth threshold circuits for division and iterated multiplication , 2002, J. Comput. Syst. Sci..

[8]  M. Ernest The history and art of change ringing , 1931 .

[9]  P. D. Tougaw,et al.  Logical devices implemented using quantum cellular automata , 1994 .

[10]  Michael Sipser,et al.  Parity, circuits, and the polynomial-time hierarchy , 1981, 22nd Annual Symposium on Foundations of Computer Science (sfcs 1981).

[11]  Eugene L. Lawler,et al.  An Approach to Multilevel Boolean Minimization , 1964, JACM.

[12]  Wolfgang J. Paul A 2.5 n-lower bound on the combinational complexity of Boolean functions , 1975, STOC '75.

[13]  Grigory Yaroslavtsev,et al.  Finding Efficient Circuits Using SAT-Solvers , 2009, SAT.

[14]  Zheng Huang,et al.  Fast Boolean matching based on NPN classification , 2013, 2013 International Conference on Field-Programmable Technology (FPT).

[15]  Yusuf Leblebici,et al.  Top–Down Fabrication of Gate-All-Around Vertically Stacked Silicon Nanowire FETs With Controllable Polarity , 2014, IEEE Transactions on Nanotechnology.

[16]  Eiichi Goto,et al.  Some Theorems Useful in Threshold Logic for Enumerating Boolean Functions , 1962, IFIP Congress.

[17]  Jin-Yi Cai,et al.  Circuit minimization problem , 2000, STOC '00.

[18]  Claus-Peter Schnorr The Combinational Complexity of Equivalence , 1976, Theor. Comput. Sci..

[19]  H.-S. Philip Wong,et al.  Combinational Logic Design Using Six-Terminal NEM Relays , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Norbert Blum A Boolean Function Requiring 3n Network Size , 1984, Theor. Comput. Sci..

[21]  Giovanni De Micheli,et al.  LUT Mapping and Optimization for Majority-Inverter Graphs , 2016 .

[22]  Giovanni De Micheli,et al.  A novel basis for logic rewriting , 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

[23]  David Thomas,et al.  The Art in Computer Programming , 2001 .

[24]  Giovanni De Micheli,et al.  Optimizing Majority-Inverter Graphs with functional hashing , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[25]  Massoud Pedram,et al.  A new canonical form for fast Boolean matching in logic synthesis and verification , 2005, Proceedings. 42nd Design Automation Conference, 2005..