Architectural evaluation of a universal host computer munap

This paper describes the architectural evaluation of a universal host computer MUNAP in terms of: (1) nonnumerical capability; (ii) multiprocessor parallelism; and (iii) flexibility of the two-level microprogramming scheme, based on the experimental results. The findings of the dynamic evaluation are summarized as follows. (i) The divide and concatenate unit is especially useful for decoding machine instructions and manipulating tags in high-level language machines so that the number of execution steps is decreased 30–40 percent. The bit operation unit is useful for numerical processing which frequently utilizes priority encoding. This provides a reduction in execution steps of 15 percent. In the shuffle exchange network, 16, 32, and 48-bit circular shifts and broadcasts are used effectively for data transfers between processor units and serial operations. (ii) The average numbers of active processor units are 3.6 - 3.8 for such numerical computations as Fast Fourier Transform, and 2.1 to 2.5 for emulations of a wide variety of high-level languages. (iii) In the two-level microprogramming scheme, the allocation ratio of the nanoprogram memory increases due to word size optimization of nanoprogram memory so that 80 - 90 percent of it is used for large-scale microprograms.