Networks on Chips for High-End Consumer-Electronics TV System Architectures

Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SOCs are application-specific standard products (ASSPs) with limited programmability We describe why TV SOCs must become more flexible, and why companion chips together with networks on chips (NOC) are a crucial enabling technology In particular, networks that span multiple chips will become important in the near future. We demonstrate our ideas by extending a commercially-available SOC for picture improvement in high-end TVs with the /Ethereal NOC. Our first unoptimised results indicate that replacing the original interconnect (consisting of dedicated links and multiplexers for bypasses) by programmable NOC increases the SOC area by 4% and its power dissipation by 12%. The new, flexible SOC allows new tasks to be spliced in at any point in the task graph. Both analytical performance verification and system simulations at RTL VHDL show that the extended SOC meets its functional requirements. Using the /Ethereal design flow the extended architecture was designed, implemented, and verified in 12 person months. To the best of our knowledge, this is the first application of a NOC to a commercial SOC. The quantitative results indicate that even retrofitting a NOC to an existing architecture is beneficial at acceptable cost

[1]  Om Prakash Gangwal,et al.  Building Predictable Systems on Chip: An Analysis of Guaranteed Communication in the Aethereal Network on Chip , 2005 .

[2]  Gert Slavenburg,et al.  Processing the new world of interactive media , 1999 .

[3]  Sergei Sawitzki,et al.  A novel toolset for the development of FPGA-like reconfigurable logic , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[4]  Srinivasan Murali,et al.  Mapping and configuration methods for multi-use-case networks on chips , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[5]  Kees G. W. Goossens,et al.  An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[6]  Om Prakash Gangwal,et al.  Interconnect and Memory Organization in SOCs for Advanced Set-Top Boxes and TV , 2004 .

[7]  Jens Sparsø,et al.  A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip , 2005, Design, Automation and Test in Europe.

[8]  Richard P. Kleihorst,et al.  Power Consumption of Performance-Scaled SIMD Processors , 2004, PATMOS.

[9]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[10]  Théodore Marescaux,et al.  Centralized run-time resource management in a network-on-chip containing reconfigurable hardware tiles , 2005, Design, Automation and Test in Europe.

[11]  Hans Van Antwerpen,et al.  The Philips Nexperia Digital Video Platform , 2003 .

[12]  Srinivasan Murali,et al.  A Methodology for Mapping Multiple Use-Cases onto Networks on Chips , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[13]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[14]  Om Prakash Gangwal,et al.  Understanding video pixel processing applications for flexible implementations , 2003, Euromicro Symposium on Digital System Design, 2003. Proceedings..

[15]  Kees Goossens,et al.  Chapter 15 INTERCONNECT AND MEMORY ORGANIZATION IN SOCS FOR ADVANCED SET-TOP BOXES AND TV Evolution, Analysis, and Trends , 2005 .

[16]  Kees G. W. Goossens,et al.  A unified approach to constrained mapping and routing on network-on-chip architectures , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[17]  Orlando Moreira,et al.  Predictable Embedded Multiprocessor System Design , 2004, SCOPES.

[18]  Rudy Lauwereins,et al.  Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs , 2002, FPL.

[19]  Om Prakash Gangwal,et al.  An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration , 2005 .

[20]  S. Rathman,et al.  Processing the new world of interactive media , 1998 .

[21]  Ran Ginosar,et al.  QNoC: QoS architecture and design process for network on chip , 2004, J. Syst. Archit..

[22]  Kees G. W. Goossens,et al.  A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification , 2005, Design, Automation and Test in Europe.