On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition

To increase the flexibility of single-chip evolvable hardware systems, we explore possibilities of systems with the evolutionary algorithm implemented in software on an on-chip processor. This gives higher flexibility compared to implementing an evolutionary algorithm directly in hardware, since the parameters and behaviour of the algorithm can easily be changed, and complex operators are more feasible to implement. In this paper a Xilinx MicroBlaze soft core processor is used, and the system is implemented in a Xilinx FPGA. A suitable hardware architecture for image recognition has been proposed, and it is applied to a face recognition task. Data buses and higher level functions have been utilized in order to reduce the search space for the evolutionary algorithm. Experiments have been performed on the physical device, with software running in parallel with fitness computation in digital logic. Results show that the MicroBlaze system evolves at half the speed of a Pentium M system running at 17 times the FPGA clock frequency. The distinction of a certain face from others is performed at 94.9% accuracy. In addition, the possibilities for evolutionary adaptation over time are explored by introducing changes in the training set. The system shows ability to adapt to these changes

[1]  J. Torresen Exploring knowledge schemes for efficient evolution of hardware , 2004, Proceedings. 2004 NASA/DoD Conference on Evolvable Hardware, 2004..

[2]  Isamu Kajitani,et al.  A myoelectric controlled prosthetic hand with an evolvable hardware LSI chip , 2003 .

[3]  Jim Torresen,et al.  Two-Step Incremental Evolution of a Prosthetic Hand Controller Based on Digital Logic Gates , 2001, ICES.

[4]  Kyrre Glette,et al.  A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device , 2005, ICES.

[5]  Xin Yao,et al.  Promises and challenges of evolvable hardware , 1996, IEEE Trans. Syst. Man Cybern. Part C.

[6]  Eduardo Sanchez,et al.  An Evolving and Developing Cellular Electronic Circuit , 2004 .

[7]  Isamu Kajitani,et al.  An Evolvable Hardware Chip and Its Application as a Multi-Function Prosthetic Hand Controller , 1999, AAAI/IAAI.

[8]  Neal R. Harvey,et al.  Everything on the Chip: A Hardware-Based Self-Contained Spatially-Structured Genetic Algorithm for Signal Processing , 2000, ICES.

[9]  Gunnar Tufte,et al.  Prototyping a GA Pipeline for complete hardware evolution , 1999, Proceedings of the First NASA/DoD Workshop on Evolvable Hardware.

[10]  Sanyou Zeng,et al.  Evolvable Systems: From Biology to Hardware, 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007, Proceedings , 2007, ICES.

[11]  Lukás Sekanina,et al.  An Evolvable Image Filter: Experimental Evaluation of a Complete Hardware Implementation in FPGA , 2005, ICES.

[12]  Lukás Sekanina Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware , 2003, ICES.

[13]  Gunnar Tufte,et al.  Bridging the genotype-phenotype mapping for digital FPGAs , 2001, Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001.

[14]  Isamu Kajitani,et al.  Hardware Evolution at Function Level , 1996, PPSN.

[15]  Taro Nakamura,et al.  Genetic Algorithm-Based Methodology for Pattern Recognition Hardware , 2000, ICES.

[16]  Richard J. Carter,et al.  A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine , 2001, Genetic Programming and Evolvable Machines.

[17]  D. E. Goldberg,et al.  Genetic Algorithms in Search , 1989 .

[18]  Jim Torresen,et al.  Possibilities and Limitations of Applying Evolvable Hardware to Real-World Applications , 2000, FPL.

[19]  David E. Goldberg,et al.  Genetic Algorithms in Search Optimization and Machine Learning , 1988 .