Virtual delay vector-based core-stateless packet scheduling architecture

In existing deterministic core-stateless packet scheduling schemes, scalability is often achieved at the expense of under-utilization of the reserved bandwidth for flows at core nodes.This increases the burstiness in the traffic flow and limits the utility of network resources.The under-utilization is reduced by a core-stateless packet scheduling architecture,called the delay vector reference system.By using the virtual delay vector technique,the system provides the same end-to-end delay bound as VirtualClock and guarantees per-node accurate reserved rate allocation for each flow not just at edge nodes as with existing core-stateless schemes.Also, the system uses the partial average approach to meet a variety of accuracy and cost requirements.Additionally,these algorithms have good incremental deployability due to the similarity of operations at core nodes.