Signal Processing with High Complexity: Prototyping and Industrial Design
暂无分享,去创建一个
[1] Joseph R. Cavallaro,et al. Efficient MIMO equalization for downlink multi-code CDMA: complexity optimization and comparative study , 2004, IEEE Global Telecommunications Conference, 2004. GLOBECOM '04..
[2] Fernando Herrera,et al. System-level performance analysis in SystemC , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[3] Josep Vidal,et al. Turbo linear dispersion space time coding for MIMO HSDPA systems , 2003 .
[4] Edward A. Lee,et al. A global criticality/local phase driven algorithm for the constrained hardware/software partitioning problem , 1994, Third International Workshop on Hardware/Software Codesign.
[5] Paul E. Landman. High-level power estimation , 1996, ISLPED.
[6] E.A. Lee,et al. Synchronous data flow , 1987, Proceedings of the IEEE.
[7] Markus Rupp,et al. A Consistent Design Methodology for Wireless Embedded Systems , 2005, EURASIP J. Adv. Signal Process..
[8] Sanghamitra Roy,et al. An algorithm for trading off quantization error with hardware resources for MATLAB-based FPGA design , 2005, IEEE Transactions on Computers.
[9] Martin Shepperd,et al. Derivation and Validation of Software Metrics , 1993 .
[10] A. Jerraya,et al. Virtual Prototyping For Modular And Flexible Hardware-Software Systems , 1997, Des. Autom. Embed. Syst..
[11] Markus Rupp,et al. Static code analysis of functional descriptions in SystemC , 2006, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06).
[12] Anas N. Al-Rabadi,et al. A comparison of modified reconstructability analysis and Ashenhurst‐Curtis decomposition of Boolean functions , 2004 .
[13] Brian W. Kernighan,et al. An efficient heuristic procedure for partitioning graphs , 1970, Bell Syst. Tech. J..
[14] Rudy Lauwereins,et al. Code generation for compiled bit-true simulation of DSP applications , 1998, Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210).
[15] Edward A. Lee,et al. Overview of the Ptolemy project , 2001 .
[16] Joseph R. Cavallaro,et al. Rapid Industrial Prototyping and Scheduling of 3G/4G SoC Architectures with HLS Methodology , 2005 .
[17] Jan M. Rabaey. Low-power silicon architecture for wireless communications: embedded tutorial , 2000, ASP-DAC.
[18] Shu Hung Leung,et al. On the statistics of fixed-point roundoff error , 1985, IEEE Trans. Acoust. Speech Signal Process..
[19] Edward A. Lee,et al. Software synthesis for DSP using ptolemy , 1995, J. VLSI Signal Process..
[20] Ron Miller,et al. Behavioral Synthesis Methodology for HDL-Based Specification and Validation , 1995, 32nd Design Automation Conference.
[21] Markus Rupp,et al. Prototype experience for MIMO BLAST over third-generation wireless system , 2003, IEEE J. Sel. Areas Commun..
[22] Florian Kaltenberger,et al. A scalable rapid prototyping system for real-time MIMO OFDM transmissions , 2005 .
[23] D. Houzet,et al. Easy SoC design with VC1 SystemC adapters , 2004 .
[24] Daniel D. Gajski,et al. SPECC: Specification Language and Methodology , 2000 .
[25] Markus Rupp,et al. A Fast Rescheduling Heuristic of SDF Graphs for HW/SW Partitioning Algorithms , 2006 .
[26] Thorsten Grotker,et al. System Design with SystemC , 2002 .
[27] Jörg Henkel,et al. An approach to the adaptation of estimated cost parameters in the COSYMA system , 1994, CODES '94.
[28] Sanghamitra Roy,et al. An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design , 2004, Proceedings. 41st Design Automation Conference, 2004..
[29] O. Sentieys,et al. Design and Implementation of WCDMA Platforms : Challenges and Trade-offs � , 2003 .
[30] S. Evain,et al. μ spider: a CAD tool for efficient NoC design , 2004, Proceedings Norchip Conference, 2004..
[31] Jean Paul Calvez,et al. A Graphical Tool for System-Level Modeling and Simulation with SystemC , 2003, FDL.
[32] Y. Neuvo,et al. Cellular phones as embedded systems , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
[33] R. B. Kearfott,et al. Interval Computations: Introduction, Uses, and Resources , 2000 .
[34] Jean-Philippe Diguet,et al. Design Trotter : Building and Selecting Architectures for Embedded Multimedia Applications , 2003 .
[35] Frank D. Anger,et al. Scheduling Precedence Graphs in Systems with Interprocessor Communication Times , 1989, SIAM J. Comput..
[36] Jörg Henkel,et al. A hardware/software partitioner using a dynamically determined granularity , 1997, DAC.
[37] Luciano Lavagno,et al. Hardware-software co-design of embedded systems: the POLIS approach , 1997 .
[38] Yves Sorel,et al. From algorithm and architecture specifications to automatic generation of distributed real-time executives: a seamless flow of graphs transformations , 2003, First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings..
[39] W. Luk,et al. Truncation noise in fixed-point SFGs [digital filters] , 1999 .
[40] Frédéric Boussinot,et al. The ESTEREL language , 1991, Proc. IEEE.
[41] Hugo De Man,et al. Operating system based software generation for systems-on-chip , 2000, Proceedings 37th Design Automation Conference.
[42] C. Scott Ananian,et al. Silicon c: a hardware backend for suif , 1998 .
[43] Nikil D. Dutt,et al. SPARK: a high-level synthesis framework for applying parallelizing compiler transformations , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..
[44] Romuald Rocher,et al. Automatic SQNR determination in non-linear and non-recursive fixed-point systems , 2004, 2004 12th European Signal Processing Conference.
[45] W. Luk,et al. Truncation noise in fixed-point SFGs , 1999 .
[46] Ranga Vemuri,et al. An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling , 2000, Des. Autom. Embed. Syst..
[47] André Bourdoux,et al. From MIMO-OFDM Algorithms to a Real-Time Wireless Prototype: A Systematic Matlab-to-Hardware Design Flow , 2006, EURASIP J. Adv. Signal Process..
[48] Mark Stephenson,et al. Bidwidth analysis with application to silicon compilation , 2000, PLDI '00.
[49] Dominique Houzet,et al. Easy SoC design with VC1 SystemC adapters , 2004, Euromicro Symposium on Digital System Design, 2004. DSD 2004..
[50] Sotirios G. Ziavras,et al. Coprocessor design to support MPI primitives in configurable multiprocessors , 2007 .
[51] Reinaldo A. Valenzuela,et al. Detection algorithm and initial laboratory results using V-BLAST space-time communication architecture , 1999 .
[52] T. C. Hu. Parallel Sequencing and Assembly Line Problems , 1961 .
[53] S. Haykin,et al. Adaptive Filter Theory , 1986 .
[54] J. Hausner,et al. Implementation of signal processing algorithms for 3G and beyond , 2003, IEEE Microwave and Wireless Components Letters.
[55] T. Moon,et al. Mathematical Methods and Algorithms for Signal Processing , 1999 .
[56] C. D. Gelatt,et al. Optimization by Simulated Annealing , 1983, Science.
[57] Markus Rupp,et al. Automated floating-point to fixed-point conversion with the fixify environment , 2005, 16th IEEE International Workshop on Rapid System Prototyping (RSP'05).
[58] Salim OUADJAOUT,et al. VSIA interface cosynthesis , 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.
[59] Gabor Karsai,et al. Model-integrated development of embedded software , 2003, Proc. IEEE.
[60] Edward A. Lee,et al. The extended partitioning problem: hardware/software mapping and implementation-bin selection , 1995, Proceedings Sixth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype.
[61] G.E. Moore,et al. Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.
[62] Heidi Steendam,et al. The effect of clock frequency offsets on downlink MC-DS-CDMA , 2002, IEEE Seventh International Symposium on Spread Spectrum Techniques and Applications,.
[63] Donatella Sciuto,et al. Metrics for design space exploration of heterogeneous multiprocessor embedded systems , 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).
[64] Farid N. Najm,et al. High-level area estimation , 2002, ISLPED '02.
[65] Axel Jantsch,et al. FPGA resource and timing estimation from Matlab execution traces , 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).
[66] V. K. Jain,et al. VLSI architecture for an advance DS/CDMA wireless communication receiver , 1997, 1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon.
[67] Barry W. Boehm,et al. Software Engineering Economics , 1993, IEEE Transactions on Software Engineering.
[68] A. W. M. van den Enden,et al. Discrete Time Signal Processing , 1989 .
[69] Yun Cao,et al. Quality-driven design by bitwidth optimization for video applications , 2003, ASP-DAC '03.
[70] Juraj Hromkovic,et al. Algorithmics for Hard Problems , 2002, Texts in Theoretical Computer Science An EATCS Series.
[71] William Fornaciari,et al. An area estimation methodology for FPGA based designs at systemc-level , 2004, Proceedings. 41st Design Automation Conference, 2004..
[72] Y. Guo,et al. Compact hardware accelerator for functional verification and rapid prototyping of 4G wireless communication systems , 2004, Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004..
[73] Wolfgang Klingauf. Systematic transaction level modeling of embedded systems with SystemC , 2005, Design, Automation and Test in Europe.
[74] M. Holzer,et al. Fast Rescheduling of Multi-Rate Systems for HW/SW Partitioning Algorithms , 2005, Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005..
[75] Johan Cockx,et al. Efficient modeling of preemption in a virtual prototype , 2000, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668).
[76] Frank Vahid,et al. Extending the Kernighan/Lin Heuristic for Hardware and Software Functional Partitioning , 1997, Des. Autom. Embed. Syst..
[77] Erwin A. de Kock,et al. COSY communication IP's , 2000, Proceedings 37th Design Automation Conference.
[78] Matti Latva-aho,et al. Chip-Level Channel Equalization in WCDMA Downlink , 2002, EURASIP J. Adv. Signal Process..
[79] Gerard J. Foschini,et al. Layered space-time architecture for wireless communication in a fading environment when using multi-element antennas , 1996, Bell Labs Technical Journal.
[80] R. Subramanian. Shannon vs Moore: driving the evolution of signal processing platforms in wireless communications , 2002, IEEE Workshop on Signal Processing Systems.
[81] M. Rupp,et al. Static Estimation of Execution Times for Hardware Accelerators in System-on-Chips , 2005, 2005 International Symposium on System-on-Chip.
[82] Romuald Rocher,et al. Accuracy evaluation of fixed-point LMS algorithm , 2004, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing.
[83] Robert W. Brodersen,et al. An automated floating-point to fixed-point conversion methodology , 2003, 2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03)..
[84] Fernando Herrera,et al. Single Source Design Environment for Embedded Systems Based on SystemC , 2004, Des. Autom. Embed. Syst..
[85] B. Widrow. Statistical analysis of amplitude-quantized sampled-data systems , 1961, Transactions of the American Institute of Electrical Engineers, Part II: Applications and Industry.
[86] Adrian Evans,et al. Functional verification of large ASICs , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[87] Tor Aulin,et al. Breadth-first maximum likelihood sequence detection: basics , 1999, IEEE Trans. Commun..
[88] Markus Rupp,et al. Design flow improvements for embedded wireless receivers , 2004, 2004 12th European Signal Processing Conference.
[89] Rob A. Rutenbar,et al. Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs , 2003, ICCAD 2003.
[90] D. Gajski,et al. Transaction Level Modeling in System Level Design , 2003 .
[91] Richard Hersemeule,et al. Fast prototyping: a system design flow for fast design, prototyping and efficient IP reuse , 1999, Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450).
[92] Keshab K. Parhi,et al. High-level DSP synthesis using concurrent transformations, scheduling, and allocation , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[93] Sharad Malik,et al. A Survey of Optimization Techniques Targeting Low Power VLSI Circuits , 1995, 32nd Design Automation Conference.
[94] Seehyun Kim,et al. Fixed-point optimization utility for C and C++ based digital signal processing programs , 1998 .
[95] Markus Rupp,et al. HW/SW Partitioning Using High Level Metrics , 2004 .
[96] A. Kumar,et al. A multiplier generator for Xilinx FPGAs , 1996, Proceedings of 9th International Conference on VLSI Design.
[97] Markus Rupp,et al. A Fully Automated Environment for Verification of Virtual Prototypes , 2006, EURASIP J. Adv. Signal Process..
[98] François Charot,et al. Automatic floating-point to fixed-point conversion for DSP code generation , 2002, CASES '02.
[99] Jiang Yue,et al. Channel estimation and data detection for MIMO-OFDM systems , 2003, GLOBECOM '03. IEEE Global Telecommunications Conference (IEEE Cat. No.03CH37489).
[100] Jörg Henkel,et al. Hardware-software cosynthesis for microcontrollers , 1993, IEEE Design & Test of Computers.
[101] Edward A. Lee,et al. The Extended Partitioning Problem: Hardware/Software Mapping, Scheduling, and Implementation-bin Selection , 1997, Des. Autom. Embed. Syst..
[102] Fernando Herrera,et al. Systemic Embedded Software Generation from SystemC , 2003, DATE.
[103] Joseph P. Poole. A Method to Determine a Basis Set of Paths to Perform Program Testing | NIST , 1995 .
[104] Daniel D. Gajski,et al. High ― Level Synthesis: Introduction to Chip and System Design , 1992 .
[105] Prithviraj Banerjee,et al. Automatic conversion of floating point MATLAB programs into fixed point FPGA based hardware design , 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..
[106] Amnon Naamad,et al. Statemate: a working environment for the development of complex reactive systems , 1988, ICSE '88.
[107] Markus Rupp,et al. Rapid prototyping for wireless designs: the five-ones approach , 2003, Signal Process..
[108] Heinrich Meyr,et al. FRIDGE: a fixed-point design and simulation environment , 1998, Proceedings Design, Automation and Test in Europe.
[109] Mickaël Raulet,et al. Rapid Prototyping for Heterogeneous Multicomponent Systems: An MPEG-4 Stream over a UMTS Communication Link , 2006, EURASIP J. Adv. Signal Process..
[110] Daniel Gajski,et al. Embedded software generation from system level design languages , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).
[111] Petru Eles,et al. System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search , 1997, Des. Autom. Embed. Syst..
[112] Robert B. Ross,et al. Using MPI-2: Advanced Features of the Message Passing Interface , 2003, CLUSTER.
[113] Gabor Karsai. Design tool integration: an exercise in semantic interoperability , 2000, Proceedings Seventh IEEE International Conference and Workshop on the Engineering of Computer-Based Systems (ECBS 2000).
[114] Theerayod Wiangtong,et al. Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware–Software Codesign , 2002, Des. Autom. Embed. Syst..
[115] Luciano Lavagno,et al. Hardware-software codesign of embedded systems , 1994, IEEE Micro.
[116] Cristina Silvano,et al. Power estimation of embedded systems: a hardware/software codesign approach , 1998, IEEE Trans. Very Large Scale Integr. Syst..
[117] Edward A. Lee,et al. A global criticality/local phase driven algorithm for the constrained hardware/software partitioning problem , 1994, CODES.
[118] Ranga Vemuri,et al. Hardware-software partitioning and pipelined scheduling of transformative applications , 2002, IEEE Trans. Very Large Scale Integr. Syst..