Octagon architecture for low power and high performance NoC design

Network-on-Chip (NoC) architectures have been shown to solve on chip communication issues in larger SoC designs, but its success heavily depends on the total power budget they may require. Designing power efficient NoCs or finding ways to reduce NoC power is thus extremely important. In this paper, power efficiency of Synchronous and Asynchronous Octagon NoC architectures is presented. The relation between ccdata (the activity factor of the data transfers between the two switches) and power efficiency of the two networks is analyzed. Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfers between two switches (celata) satisfies a particular range. The area of Asynchronous switch is increased by 25% as compared to Synchronous switch. However the power dissipation of the Asynchronous architecture is decreased by 27% in comparison to the power dissipation of the Synchronous architecture when adata equals 0.2 and the activity factor of the control signals is 1/64 of the adata. The total metal resources required to implement Asynchronous design are decreased by 4 %.

[1]  Ran Ginosar,et al.  High Rate Data Synchronization in GALS SoCs , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Hui-Fen Huang,et al.  Global interconnect width and spacing optimization for latency, bandwidth and power dissipation , 2005, IEEE Transactions on Electron Devices.

[3]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[4]  Eckhard Grass,et al.  Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook , 2007, IEEE Design & Test of Computers.

[5]  A. Alvandpour,et al.  A 5.1GHz 0.34mm2 Router for Network-on-Chip Applications , 2007, 2007 IEEE Symposium on VLSI Circuits.

[6]  Haytham Elmiligi,et al.  Power optimization for application-specific networks-on-chips: A topology-based approach , 2009, Microprocess. Microsystems.

[7]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[8]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[9]  Partha Pratim Pande,et al.  Performance evaluation and design trade-offs for network-on-chip interconnect architectures , 2005, IEEE Transactions on Computers.

[10]  Matheus T. Moreira,et al.  Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

[11]  Gursharan Reehal.  Designing Low Power and High Performance Network-on-Chip Communication Architectures for Nanometer SoCs , 2012 .

[12]  Mohamed A. Abd El-Ghany,et al.  High throughput architecture for high performance NoC , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[13]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[14]  Sujit Dey,et al.  An Interconnect Architecture for Networking Systems on Chips , 2002, IEEE Micro.