A Simple Semiempirical Short-Channel MOSFET Current–Voltage Model Continuous Across All Regions of Operation and Employing Only Physical Parameters

A simple semiempirical model ID(VGS, VDS) for short-channel MOSFETs applicable in all regions of device operation is presented. The model is based on the so-called ldquotop-of-the-barrier-transportrdquo model, and we refer to it as the ldquovirtual sourcerdquo (VS) model. The simplicity of the model comes from the fact that only ten parameters are used. Of these parameters, six are directly obtainable from standard device measurements: 1) gate capacitance in strong inversion conditions (typically at maximum voltage VGS = Vdd); 2) subthreshold swing; 3) drain-induced barrier lowering (DIBL) coefficient; 4) current in weak inversion (typically Ioff at VGS = 0 V) and at high VDS; 5) total resistance at VDS = 0 V and VGS = Vdd and 6), effective channel length. Three fitted physical parameters are as follows: 1) carrier low-field effective mobility; 2) parasitic source/drain resistance, 3) the saturation region carrier velocity at the so-called virtual source. Lastly, a constrained saturation-transition-region empirical parameter is also fitted. The modeled current versus voltage characteristics and their derivatives are continuous from weak to strong inversion and from the linear to saturation regimes of operation. Remarkable agreement with published state-of-the-art planar short-channel strained devices is demonstrated using physically meaningful values of the fitted physical parameters. Moreover, the model allows for good physical insight in device performance properties, such as extraction of the VSV, which is a parameter of critical technological importance that allows for continued MOSFET performance scaling. The simplicity of the model and the fact that it only uses physically meaningful parameters provides an easy way for technology benchmarking and performance projection.

[1]  D. F. Nelson,et al.  High‐field drift velocity of electrons at the Si–SiO2 interface as determined by a time‐of‐flight technique , 1983 .

[2]  L. T. Su,et al.  A study of deep-submicron MOSFET scaling based on experiment and simulation , 1995 .

[3]  Mark S. Lundstrom Elementary scattering theory of the Si MOSFET , 1997, IEEE Electron Device Letters.

[4]  J.A. del Alamo,et al.  Lateral and Vertical Scaling of $\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}$ HEMTs for Post-Si-CMOS Logic Applications , 2008, IEEE Transactions on Electron Devices.

[5]  Osama M. Nayfeh,et al.  Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations , 2006, IBM J. Res. Dev..

[6]  Mark Y. Liu,et al.  A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array , 2008, 2008 IEEE International Electron Devices Meeting.

[7]  R. E. Thomas,et al.  Carrier mobilities in silicon empirically related to doping and field , 1967 .

[8]  Y. Tsividis Operation and modeling of the MOS transistor , 1987 .

[9]  N. D. Arora,et al.  MOSFET Models for VLSI Circuit Simulation: Theory and Practice , 1993 .

[10]  D. Antoniadis,et al.  On experimental determination of carrier velocity in deeply scaled NMOS: how close to the thermal limit? , 2001, IEEE Electron Device Letters.

[11]  D.A. Antoniadis,et al.  Transistor Performance Scaling: The Role of Virtual Source Velocity and Its Mobility Dependence , 2006, 2006 International Electron Devices Meeting.

[12]  D.A. Antoniadis,et al.  The future of high-performance CMOS: Trends and requirements , 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

[13]  R. W. Coen,et al.  Velocity of surface carriers in inversion layers on silicon , 1980 .

[14]  P. Bai,et al.  An advanced low power, high performance, strained channel 65nm technology , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[15]  D.A. Antoniadis,et al.  MOSFET Performance Scaling—Part II: Future Directions , 2008, IEEE Transactions on Electron Devices.

[16]  Mansun Chan,et al.  A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation , 1997 .

[17]  Mark S. Lundstrom,et al.  Essential physics of carrier transport in nanoscale MOSFETs , 2000, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502).

[18]  D.A. Antoniadis,et al.  MOSFET Performance Scaling—Part I: Historical Trends , 2008, IEEE Transactions on Electron Devices.

[19]  G. T. Wright,et al.  Threshold modelling of MOSFETs for CAD of CMOS-VLSI , 1985 .