2 A 2 . 5 Gb / s Multi-Rate 0 . 25 μ m CMOS CDR Utilizing a Hybrid Analog / Digital Loop Filter

A CDR architecture is presented in 0.25μm CMOS that leverages a fully integrated hybrid analog/digital loop-filter structure to achieve the desired jitter performance with low area and power consumption while also allowing multi-rate operation at 155, 622, 1250, and 2500Mb/s data rates. The overall CDR performance exceeds SONET requirements. The small package size of the CDR chip and the elimination of sensitive noise-entry points at package pins due to full integration of the loop filter simplifies the board design. In this paper, key techniques for the implementation of the hybrid loop filter, including a phase-to-digital converter and digital decimator, are described.