Realistic Fault Modeling for VLSI Testing

Functional failures of VLSI circuits are caused by process-induced defects. Such defects have very complex physical characteristics and may be significantly different from the simplistic defect models assumed by typical fault modeling techniques. In the tutorial an overview of the actual mechanisms causing processing defects, and the defects' electrical manifestations will be discussed. It will be demonstrated that inadequate insight into the physics of processing defects and the manufacturing process may lead to inefficient testing of actual VLSI circuits.

[1]  John Paul Shen,et al.  Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells , 1984, ITC.

[2]  R. L. Wadsack,et al.  Fault modeling and logic simulation of CMOS and MOS integrated circuits , 1978, The Bell System Technical Journal.

[3]  C.H. Stapper,et al.  Integrated circuit yield statistics , 1983, Proceedings of the IEEE.

[4]  D. M. H. Walker,et al.  VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Wojciech Maly,et al.  Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  C. Stapper.  Yield model for 256K RAMs and beyond , 1982, 1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[7]  Duncan M. Walker.  Yield simulation for integrated circuits , 1987 .

[8]  Yves Crouzet,et al.  Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability , 1980, IEEE Transactions on Computers.

[9]  Charles H. Stapper,et al.  Modeling of Integrated Circuit Defect Sensitivities , 1983, IBM J. Res. Dev..

[10]  P. Gangatirkar,et al.  Test/characterization procedures for high density silicon RAMs , 1982, 1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[11]  Carlo H. Séquin,et al.  Design and Application of Self-Testing Comparators Implemented with MOS PLA's , 1984, IEEE Transactions on Computers.

[12]  Andrzej J. Strojwas,et al.  VLSI Yield Prediction and Estimation: A Unified Framework , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Duncan Moore Henry Walker.  Yield simulation for integrated circuits (fault analysis, redundancy analysis, fabrication defects) , 1986 .

[14]  Wojciech Maly,et al.  Yield estimation model for VLSI artwork evaluation , 1983 .

[15]  N. S. Barnett,et al.  Private communication , 1969 .

[16]  Hideo Fujiwara,et al.  Logic Testing and Design for Testability , 1985 .

[17]  John Paul Shen,et al.  Inductive Fault Analysis of MOS Integrated Circuits , 1985, IEEE Design & Test of Computers.