Modeling of cylindrical surrounding gate MOSFETs including the fringing field effects
暂无分享,去创建一个
[1] Santosh Kumar Gupta. Modeling of Built-In Potential Variations of Cylindrical Surrounding Gate (CSG) MOSFETs , 2012, VLSIC 2012.
[2] H. B. Dwight,et al. Tables of Integrals and Other Mathematical Data , 1934 .
[3] Ru Huang,et al. Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs , 2011, IEEE Transactions on Electron Devices.
[4] J. G. Fossum,et al. Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs , 2002 .
[5] Hyuck-In Kwon,et al. A full analytical model of fringing-field-induced parasitic capacitance for nano-scaled MOSFETs , 2010 .
[6] Jyh-Chyurn Guo,et al. A New Three-Dimensional Capacitor Model for Accurate Simulation of Parasitic Capacitances in Nanoscale MOSFETs , 2009, IEEE Transactions on Electron Devices.
[7] O. Faynot,et al. A Model of Fringing Fields in Short-Channel Planar and Triple-Gate SOI MOSFETs , 2007, IEEE Transactions on Electron Devices.
[8] D. Jimenez,et al. Analytical Charge and Capacitance Models of Undoped Cylindrical Surrounding-Gate MOSFETs , 2007, IEEE Transactions on Electron Devices.
[9] K. K. Young. Analysis of conduction in fully depleted SOI MOSFETs , 1989 .
[10] B. Iñíguez,et al. Continuous analytic I-V model for surrounding-gate MOSFETs , 2004, IEEE Electron Device Letters.
[11] D. Faycal,et al. Surface- potential- based model to study the subthreshold swing behavior including hot-carrier effect for nanoscale GASGAA MOSFETs , 2009, 5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era.
[12] S. Narendra,et al. Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors , 2003 .
[13] Abhinav Kranti,et al. Analytical model for threshold voltage and I-V characteristics of fully depleted short channel cylindrical/surrounding gate MOSFET , 2001 .
[14] R. Gupta,et al. An analytical threshold voltage model for graded channel asymmetric gate stack (GCASYMGAS) surrounding gate MOSFET , 2008 .
[15] R. Romer,et al. Tables of functions with formulae and curves , 1934 .
[16] T. Chiang. Concise Analytical Threshold Voltage Model for Cylindrical Fully Depleted Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistors , 2005 .
[17] Ru Huang,et al. Predictive modeling of capacitance and resistance in gate-all-around cylindrical nanowire MOSFETs for parasitic design optimization , 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.
[18] W. Byerly. Elements of the Integral Calculus: With a Key to the Solution of Differential Equations, and a Short Table of Integrals , 2007 .
[19] E. Greeneich,et al. An analytical model for the gate capacitance of small-geometry MOS structures , 1983, IEEE Transactions on Electron Devices.
[20] J. W. Brown,et al. Complex Variables and Applications , 1985 .
[21] Chandan Kumar Sarkar,et al. A new analytical subthreshold model of SRG MOSFET with analogue performance investigation , 2012 .
[22] G. Temple. Static and Dynamic Electricity , 1940, Nature.
[23] H. Kober,et al. Dictionary of conformal representations , 1957 .
[24] J. Plummer,et al. Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's , 1997, IEEE Electron Device Letters.
[25] R. Shrivastava,et al. A simple model for the overlap capacitance of a VLSI MOS device , 1982, IEEE Transactions on Electron Devices.
[26] Wei Wang,et al. Modeling of Gate Current and Capacitance in Nanoscale-MOS Structures , 2006, IEEE Transactions on Electron Devices.
[27] M.J. Kumar,et al. Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs , 2006, IEEE Transactions on Electron Devices.
[28] Kunihiro Suzuki. Parasitic capacitance of submicrometer MOSFET's , 1999 .
[29] M.J. Kumar,et al. On the parasitic gate capacitance of small-geometry MOSFETs , 2005, IEEE Transactions on Electron Devices.
[30] Chandan Kumar Sarkar,et al. Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model , 2012 .
[31] B.C. Paul,et al. Modeling and optimization of fringe capacitance of nanoscale DGMOS devices , 2005, IEEE Transactions on Electron Devices.
[32] Jin He,et al. Analytic Carrier-Based Charge and Capacitance Model for Long-Channel Undoped Surrounding-Gate MOSFETs , 2007, IEEE Transactions on Electron Devices.