Watermarking layout topologies

Watermarking is a technique currently being developed to effectively protect intellectual property of various types. In this paper a formalization of the watermarking problem is presented in the context of IC physical design. A class of algorithms is proposed for implanting arbitrary codes in the inherent structure of layout topologies. Similarly, a method is given to reconstruct the original watermark for a given design. The concepts of robustness against forgery and theft tracking are analyzed in light of the proposed algorithms. Examples show the suitability of the approach.

[1]  Telle Elizabeth Whitney.  Hierarchical composition of vlsi circuits , 1985 .

[2]  Yoji Kajitani,et al.  VLSI module placement based on rectangle-packing by the sequence-pair , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Michael Ian Shamos,et al.  Computational geometry: an introduction , 1985 .

[4]  H. Murata,et al.  Rectangle-packing-based module placement , 1995, ICCAD 1995.

[5]  Ralph H. J. M. Otten,et al.  Automatic Floorplan Design , 1982, 19th Design Automation Conference.

[6]  H. R. Madhusudan.  Digital watermarks , 1998 .

[7]  Edoardo Charbon.  Hierarchical watermarking in IC design , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[8]  F. Frances Yao,et al.  Computational Geometry , 1991, Handbook of Theoretical Computer Science, Volume A: Algorithms and Complexity.

[9]  JOHN VALAINIS,et al.  Two-dimensional IC layout compaction based on topological design rule checking , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..