Using simulation and genetic algorithms to improve cluster tool performance

Cluster tools have gained importance in the fabrication semiconductor chips during the last decade. Especially upcoming 300 mm fabs, they will be an integral part o the production process. In a cluster tool, several process steps required to produce a semiconductor chip are in grated into a single piece of equipment. In this way, th probability of contamination of the wafers, the space r quired for equipment, and waiting and transport times a reduced. Performance analysis of these tools is not straightfo ward and cannot be accomplished using simple analy approaches like spreadsheets. Instead, a performance a ysis tool that predicts cycle times of wafers in a cluster to adequately has to take into account the effects of differe wafer recipes, cluster tool control and architecture, wa waiting times, and sequencing. Hence, cluster tools ma for an excellent area for the application of simulation. There are already a number of publications availab that deal with the simulation and analysis of cluster too In (Atherton et al. 1990), potential throughput advantag of cluster tools and the problem of shifting bottlenecks a discussed. Pierce and Drevna (1992) and LeBaron a Pool (1994) present simulation models of cluster tools th were developed using general purpose simulation languag In (Mauer and Schelasin 1993) and (Mauer and Schela 1994), a general purpose simulation language has b